US2002069523A1PendingUtilityA1

Mounting structure of integrated circuit device having high effect of buffering stress and high reliability of connection by solder and method of mounting the same

Assignee: NEC CORPPriority: Jun 17, 1999Filed: Jan 22, 2002Published: Jun 13, 2002
Est. expiryJun 17, 2019(expired)· nominal 20-yr term from priority
Inventors:Osamu Arai
H05K 2203/1147H05K 2201/094Y10T29/49144Y10T29/49126H05K 2201/10378H05K 2201/09781H05K 3/284H05K 3/3436H05K 2201/10674H05K 2201/10977H05K 2201/049H10W 90/734H10W 90/724H10W 74/15H10W 90/701H10W 90/401H10W 42/25H05K 3/346H10W 42/121Y02P70/50
40
PatentIndex Score
0
Cited by
0
References
0
Claims

Abstract

A mounting structure of an integrated circuit device includes an integrated circuit device, a mounting board, a first solder bump, and a second solder bump. The integrated circuit device is mounted on the mounting board. The interposer board is interposed between the integrated circuit device and the mounting board. The first solder bump electrically connects the interposer board to the mounting board. The first solder bump is provided between the interposer board and the mounting board. The second solder bump buffers a stress. The second solder bump is provided between the interposer board and the mounting board.

Claims

exact text as granted — not AI-modified
What is claimed:  
     
         1 . A mounting method of an integrated circuit device, comprising: 
 (a) providing an interposer board, a plurality of through holes being formed in said interposer board;    (b) connecting an integrated circuit device to said interposer board at a position of each of said plurality of through holes;    (c) providing a plurality of first solder bumps on a mounting board at a plurality of first specific positions corresponding to said plurality of through holes when said mounting board is connected to said interposer board;    (d) providing a plurality of second solder bumps on said mounting board at a plurality of second specific positions other than said first specific positions; and    (e) connecting said mounting board to said interposer board by said first and second solder bumps, and wherein said (c) and (d) steps are performed at a substantially same time with each other.    
     
     
         2 . A mounting method of an integrated circuit device according to  claim 1 , wherein said (b) step includes connecting said integrated circuit device to said interposer board by a third solder bump provided at said position of each of said plurality of through holes and injecting a specific resin to buffer a stress at a position other than positions in which a plurality of said third solder bumps are provided.  
     
     
         3 . A mounting method of an integrated circuit device according to  claim 2 , wherein said (b) step includes providing said third solder bump having a melting point higher than those of said first and second solder bumps, and said (e) step includes melting said first and second solder bumps such that said third solder bump is not melted.  
     
     
         4 . A mounting method of an integrated circuit device according to  claim 1 , wherein said (d) step includes providing said plurality of second bumps inside said plurality of first solder bumps on said mounting board.

Join the waitlist — get patent alerts

Track US2002069523A1 — get alerts on status changes and closely related new filings.

We store only your email — no account needed. See our privacy policy.