Method of forming unlanded via

Abstract

A method of forming an unlanded via. A substrate having a conductive wire thereon is provided. An etching stop spacer is formed on each sidewall of the conductive wire. An inter-metal dielectric layer is formed over the substrate. The inter-metal dielectric layer is patterned to form a via opening that exposes the conductive wire and then a metal plug that occupies the entire via hole is formed.

What is claimed is:  
     
         1 . A method of forming an unlanded via, comprising the steps of: 
 providing a substrate having a conductive wire therein; 
 forming an etching stop spacer on each sidewall of the conductive wire;  
   forming an inter-metal dielectric layer over the substrate; 
 patterning the inter-metal dielectric layer to form a via hole that exposes the conductive wire; and  
   forming a metal plug that occupies the entire via hole.    
     
     
         2 . The method of  claim 1 , wherein material constituting the etching stop spacer includes silicon carbide.  
     
     
         3 . The method of  claim 1 , wherein material constituting the inter-metal dielectric layer includes a spin-coated low dielectric constant compound.  
     
     
         4 . The method of  claim 3 , wherein the spin-coated low dielectric constant compound includes hydrogen silsesquioxane (HSQ).  
     
     
         5 . The method of  claim 3 , wherein the spin-coated low dielectric constant compound includes methylsilsesquioxane (MSQ).  
     
     
         6 . The method of  claim 1 , wherein after the step of forming the inter-metal dielectric layer, further includes forming an insulation layer over the inter-metal dielectric layer.  
     
     
         7 . The method of  claim 6 , wherein the step of forming the insulation layer includes performing a plasma-assisted chemical vapor deposition to form a silicon dioxide layer.  
     
     
         8 . The method of  claim 7 , wherein the step of performing plasma-assisted chemical vapor deposition includes using tetra-ethyl-ortho-silicate (TEOS) as a gaseous reactant.  
     
     
         9 . The method of  claim 1 , wherein the etching stop spacers and the inter-metal dielectric layer has different etching rates.  
     
     
         10 . The method of  claim 1 , wherein the step of forming the via hole includes dry etching.  
     
     
         11 . The method of  claim 1 , wherein material constituting the metal plug includes tungsten.  
     
     
         12 . A method of forming an unlanded via, comprising the steps of: 
 providing a substrate having a conductive wire therein;    forming silicon carbide spacers on the sidewalls of the conductive wire;    forming a silsesquioxane layer over the substrate;    forming an insulation layer over the silsesquioxane layer; 
 patterning the insulation layer and the silsesquioxane layer to form a via hole that exposes the conductive wire; and  
   forming a metal plug that occupies the entire via hole.    
     
     
         13 . The method of  claim 12 , wherein material constituting the silsesquioxane layer includes hydrogen silsesquioxane (HSQ).  
     
     
         14 . The method of  claim 12 , wherein material constituting the silsesquioxane layer includes methylsilsesquioxane (MSQ).  
     
     
         15 . The method of  claim 12 , wherein the step of forming the insulation layer includes performing a plasma-assisted chemical vapor deposition to form a silicon dioxide layer.  
     
     
         16 . The method of  claim 15 , wherein the step of performing plasma-assisted chemical vapor deposition includes using tetra-ethyl-ortho-silicate (TEOS) as a gaseous reactant.  
     
     
         17 . The method of  claim 12 , wherein the silicon carbide spacers and the silsesquioxane layer has different etching rates.  
     
     
         18 . The method of  claim 12 , wherein the step of forming the via hole includes dry etching.  
     
     
         19 . The method of  claim 12 , wherein material constituting the metal plug includes tungsten.