Heterojunction bipolar transistor and method of producing the same

Abstract

A heterojunction bipolar transistor of the present invention is produced from a wafer including a substrate and a collector layer of a first conductivity type, a base layer of a second conductivity type and an emitter layer of the first conductivity type sequentially laminated on the substrate in this order. First, the wafer is etched up to a preselected depth of the collector layer via a first photoresist, which is formed at a preselected position on the emitter layer, serving as a mask. Subsequently, the collector layer etched with at least the sidewalls of the base layer and collector layer, which are exposed by the first etching step, and a second photoresist covering part of the surface of the collector layer contiguous with the sidewalls serving as a mask.

What is claimed is:  
     
         1 . A method of producing a heterojunction bipolar transistor (HBT) from a wafer consisting of a substrate and a collector layer of a first conductivity type, a base layer of a second conductivity type and an emitter layer of said first conductivity type sequentially laminated on said substrate in this order, said method comprising: 
 a first etching step of etching said wafer up to a preselected depth of said collector layer by using a first photoresist, which is formed at a preselected position on said emitter layer, as a mask; and    a second etching step of etching said collector layer by using at least a sidewall of said base layer and a sidewall of said collector layer exposed by said first etching step and a second photoresist covering a part of a surface of said collector layer contiguous with the sidewalls as a mask.    
     
     
         2 . The method as claimed in  claim 1 , further comprising: 
 a step of removing, before forming said second photoresist, said first photoresist and then forming an SiN film on said substrate; and    a step of removing, after forming said second photoresist, said SiN film exposed.    
     
     
         3 . The method as claimed in  claim 1 , further comprising: 
 a step of forming, before forming said first photoresist, an SiN film on said substrate; and    removing, after forming said first photoresist, said SiN film exposed.    
     
     
         4 . The method as claimed in  claim 3 , further comprising: 
 a step of removing, before forming said second photoresist, said first photoresist and then forming an SiN film on said substrate; and    a step of removing, after forming said second photoresist, said SiN film exposed.    
     
     
         5 . The method as claimed in  claim 1 , further comprising a step of forming at a preselected position on said emitter electrode a base electrode extending throughout said emitter layer to be thereby electrically connected to said base layer.  
     
     
         6 . The method as claimed in  claim 5 , further comprising: 
 a step of removing, before forming said second photoresist, said first photoresist and then forming an SiN film on said substrate; and    a step of removing, after forming said second photoresist, said SiN film exposed.    
     
     
         7 . The method as claimed in  claim 5 , further comprising: 
 a step of forming, before forming said first photoresist, an SiN film on said substrate; and    removing, after forming said first photoresist, said SiN film exposed.    
     
     
         8 . The method as claimed in  claim 7 , further comprising: 
 a step of removing, before forming said second photoresist, said first photoresist and then forming an SiN film on said substrate; and    a step of removing, after forming said second photoresist, said SiN film exposed.    
     
     
         9 . A method of producing an HBT from a wafer consisting of a substrate and a first collector layer of a first conductivity type, an etching stopper layer for preventing said first collector layer from being etched, a second collector layer of said first conductivity type, a base layer of a second conductivity type and an emitter layer of said first conductivity type sequentially laminated on said substrate in this order, said method comprising: 
 a first etching step of etching said wafer to a depth where said etching stopper layer is exposed by using a first photoresist formed at a preselected position on said emitter layer as a mask; and    a second etching step of etching said etching stopper layer and said first collector layer, which are exposed, by using at least a sidewall of said base layer and a sidewall of said second collector layer and a second photoresist covering a part of a surface of said etching stopper layer contiguous with the sidewalls as a mask.    
     
     
         10 . The method as claimed in  claim 9 , further comprising: 
 a step of removing, before forming said second photoresist, said first photoresist and then forming an SiN film on said substrate; and    a step of removing, after forming said second photoresist, said SiN film exposed.    
     
     
         11 . The method as claimed in  claim 9 , further comprising: 
 a step of forming, before forming said first photoresist, an SiN film on said substrate; and    removing, after forming said first photoresist, said SiN film exposed.    
     
     
         12 . The method as claimed in  claim 11 , further comprising: 
 a step of removing, before forming said second photoresist, said first photoresist and then forming an SiN film on said substrate; and    a step of removing, after forming said second photoresist, said SiN film exposed.    
     
     
         13 . The method as claimed in  claim 9 , further comprising a step of forming at a preselected position on said emitter electrode a base electrode extending throughout said emitter layer to be thereby electrically connected to said base layer.  
     
     
         14 . The method as claimed in  claim 13 , further comprising: 
 a step of removing, before forming said second photoresist, said first photoresist and then forming an SiN film on said substrate; and    a step of removing, after forming said second photoresist, said SiN film exposed.    
     
     
         15 . The method as claimed in  claim 13 , further comprising: 
 a step of forming, before forming said first photoresist, an SiN film on said substrate; and    removing, after forming said first photoresist, said SiN film exposed.    
     
     
         16 . The method as claimed in  claim 15 , further comprising: 
 a step of removing, before forming said second photoresist, said first photoresist and then forming an SiN film on said substrate; and    a step of removing, after forming said second photoresist, said SiN film exposed.    
     
     
         17 . A method of producing an HBT from a wafer consisting of a substrate and a first collector layer of a first conductivity type, a second collector layer of said first conductivity type, a base layer of a second conductivity type and an emitter layer of said first conductivity type sequentially laminated on said substrate in this order, said method comprising: 
 a first etching step of etching said wafer to a depth where said first collector layer is exposed by using a first photoresist formed at a preselected position on said emitter layer as a mask; and    a second etching step of etching said first collector layer, which is exposed, by using a sidewall of said base layer and a sidewall of said second collector layer and a second photoresist covering a part of a surface of said first collector layer contiguous with the sidewalls as a mask.    
     
     
         18 . The method as claimed in  claim 17 , further comprising: 
 a step of removing, before forming said second photoresist, said first photoresist and then forming an SiN film on said substrate; and    a step of removing, after forming said second photoresist, said SiN film exposed.    
     
     
         19 . The method as claimed in  claim 17 , further comprising: 
 a step of forming, before forming said first photoresist, an SiN film on said substrate; and    removing, after forming said first photoresist, said SiN film exposed.    
     
     
         20 . The method as claimed in  claim 19 , further comprising: 
 a step of removing, before forming said second photoresist, said first photoresist and then forming an SiN film on said substrate; and    a step of removing, after forming said second photoresist, said SiN film exposed.    
     
     
         21 . The method as claimed in  claim 17 , further comprising a step of forming at a preselected position on said emitter electrode a base electrode extending throughout said emitter layer to be thereby electrically connected to said base layer.  
     
     
         22 . The method as claimed in  claim 21 , further comprising: 
 a step of removing, before forming said second photoresist, said first photoresist and then forming an SiN film on said substrate; and    a step of removing, after forming said second photoresist, said SiN film exposed.    
     
     
         23 . The method as claimed in  claim 21 , further comprising: 
 a step of forming, before forming said first photoresist, an SiN film on said substrate; and    removing, after forming said first photoresist, said SiN film exposed.    
     
     
         24 . The method as claimed in  claim 23 , further comprising: 
 a step of removing, before forming said second photoresist, said first photoresist and then forming an SiN film on said substrate; and    a step of removing, after forming said second photoresist, said SiN film exposed.    
     
     
         25 . In an HBT consisting of a substrate and a collector layer of a first conductivity type, a base layer of a second conductivity type and an emitter layer of said first conductivity type sequentially laminated on said substrate in this order, a sidewall of said collector layer comprises at least one mesa step.  
     
     
         26 . The transistor as claimed in  claim 25 , wherein said emitter layer is formed of InGaP.  
     
     
         27 . The transistor as claimed in  claim 25 , wherein an SiN film is formed at a preselected position on at least said emitter layer.  
     
     
         28 . The transistor as claimed in  claim 27 , wherein said emitter layer is formed of InGaP.  
     
     
         29 . The transistor as claimed in  claim 25 , wherein a base electrode is formed at a preselected position of said emitter layer and extends throughout said emitter layer to be thereby electrically connected to said base layer.  
     
     
         30 . The transistor as claimed in  claim 29 , wherein said emitter layer is formed of InGaP.  
     
     
         31 . The transistor as claimed in  claim 29 , wherein an SiN film is formed at a preselected position on at least said emitter layer.  
     
     
         32 . The transistor as claimed in  claim 31 , wherein said emitter layer is formed of InGaP.  
     
     
         33 . In an HBT produced from a wafer consisting of a substrate and a first collector layer of a first conductivity type, an etching stopper layer for preventing said first collector layer from being etched, a second collector layer of said first conductivity type, a base layer of a second conductivity type and an emitter layer of said first conductivity type sequentially laminated on said substrate in this order, a mesa step is formed between a sidewall of said first collector layer and a sidewall of said second collector layer with said etching stopper layer forming a boundary.  
     
     
         34 . The transistor as claimed in  claim 33 , wherein said emitter layer is formed of InGaP.  
     
     
         35 . The transistor as claimed in  claim 33 , wherein an SiN film is formed at a preselected position on at least said emitter layer.  
     
     
         36 . The transistor as claimed in  claim 35 , wherein said emitter layer is formed of InGaP.  
     
     
         37 . The transistor as claimed in  claim 33 , wherein a base electrode is formed at a preselected position of said emitter layer and extends throughout said emitter layer to be thereby electrically connected to said base layer.  
     
     
         38 . The transistor as claimed in  claim 37 , wherein said emitter layer is formed of InGaP.  
     
     
         39 . The transistor as claimed in  claim 37 , wherein an SiN film is formed at a preselected position on at least said emitter layer.  
     
     
         40 . The transistor as claimed in  claim 39 , wherein said emitter layer is formed of InGaP.  
     
     
         41 . In an HBT produced from a wafer consisting of a substrate and a first collector layer of a first conductivity type, a second collector layer of said first conductivity type, a base layer of a second conductivity type and an emitter layer of said first conductivity type sequentially laminated on said substrate in this order, a mesa step is formed in the vicinity of an interface between said first collector layer and said second collector layer that intervenes between a sidewall of said first collector layer and a sidewall of said second collector layer.  
     
     
         42 . The transistor as claimed in  claim 41 , wherein said emitter layer is formed of InGaP.  
     
     
         43 . The transistor as claimed in  claim 41 , wherein an SiN film is formed at a preselected position on at least said emitter layer.  
     
     
         44 . The transistor as claimed in  claim 43 , wherein said emitter layer is formed of InGaP.  
     
     
         45 . The transistor as claimed in  claim 41 , wherein a base electrode is formed at a preselected position of said emitter layer and extends throughout said emitter layer to be thereby electrically connected to said base layer.  
     
     
         46 . The transistor as claimed in  claim 45 , wherein said emitter layer is formed of InGaP.  
     
     
         47 . The transistor as claimed in  claim 45 , wherein an SiN film is formed at a preselected position on at least said emitter layer.  
     
     
         48 . The transistor as claimed in  claim 47 , wherein said emitter layer is formed of InGaP.  
     
     
         49 . A method of producing a transistor from a wafer consisting of a substrate and a first function layer, a second function layer and a third function layer sequentially laminated on said substrate in this order, said method comprising: 
 a first etching step of etching said waver up to a preselected depth of said first function layer by using a first photoresist formed at a preselected position on said third function layer as a mask; and    a second etching step of etching said first function layer, which is exposed, by using a sidewall of said second function layer and a sidewall of said first function layer, which are exposed by said first etching step, and a second photoresist covering a part of a surface of said first function layer contiguous with the sidewalls as a mask.