Treatment of low-k dielectric films to enable patterning of deep submicron features

Abstract

Treating a low-k dielectric layer ( 104 ) using a highly oxidizing wet solution (e.g., H 2 O 2 ) to improve patterning. Resist poisoning occurs due to an interaction between low-k films ( 104 ), such as OSG, and DUV resist ( 130,132 ). The wet treatment is performed to either pre-treat a low-k dielectric ( 104 ) before forming the pattern ( 130,132 ) or during a rework of the pattern ( 130,132 ) to reduce resist poisoning.

1 . A method for fabricating an integrated circuit, comprising the steps of: 
 forming a low-k dielectric layer over a semiconductor body;    treating a surface of said low-k dielectric layer with a highly oxidizing wet solution;    forming a resist pattern over said low-k dielectric layer; and    etching said low-k dielectric layer using said resist pattern.    
     
     
         2 . The method of  claim 1 , wherein said highly oxidizing wet solution comprises H 2 O 2 .  
     
     
         3 . The method of  claim 1 , wherein said highly oxidizing wet solution is selected from the group consisting of H 2 SO 4 :H 2 O 2 , HNO 3 :H 2 O 2 , H 2 O 2 :H 2 O, and O 3 :H 2 O.  
     
     
         4 . The method of  claim 1 , wherein said low-k dielectric layer comprises organo-silicate glass.  
     
     
         5 . The method of  claim 1 , wherein said low-k dielectric layer comprises an ultralow-k dielectric layer having a dielectric constant less than 2.5.  
     
     
         6 . The method of  claim 1 , wherein said treating step occurs prior to forming said resist pattern.  
     
     
         7 . The method of  claim 1 , wherein said treating step removes said resist pattern as part of a pattern re-work step.  
     
     
         8 . A method of fabricating an integrated circuit having copper metal interconnects, comprising the steps of: 
 forming an interlevel dielectric (ILD) over a semiconductor body;    forming an intrametal dielectric (IMD) over the ILD;    oxidizing said IMD with a highly oxidizing wet solution;    forming a via resist pattern over said IMD;    etching a via in said IMD and ILD using said via resist pattern;    at least partially filling said via with a material;    forming a trench resist pattern over said IMD;    etching a trench in said IMD using said trench resist pattern;    removing said trench resist pattern and said material in said via; and    forming a copper interconnect in said via and said trench.    
     
     
         9 . The method of  claim 8 , wherein said highly oxidizing wet solution comprises H 2 O 2 .  
     
     
         10 . The method of  claim 8 , wherein said highly oxidizing wet solution is selected from the group consisting of H 2 SO 4 :H 2 O 2 , HNO 3 :H 2 O 2 , H 2 O 2 :H 2 O, and O 3 :H 2 O.  
     
     
         11 . The method of  claim 8 , wherein said oxidizing step occurs prior to the step of forming the via resist pattern.  
     
     
         12 . The method of  claim 11 , further comprising the step of additionally treating the IMD using a highly oxidizing wet solution after said step of at least partially filling the via and prior to the step of etching the trench.  
     
     
         13 . The method of  claim 8 , wherein said oxidizing step occurs after the step of forming the via resist pattern as part of a pattern re-work step.  
     
     
         14 . The method of  claim 8 , wherein said oxidizing step occurs after said step of at least partially filling the via and prior to the step of etching the trench.