Single event upset immune logic family

Abstract

A collection of logic gates that provide single event upset (SEU) immunity. The family of gates include an inverter, a two-input NOR gate, a two-input NAND gate, a three-input AND-NOR gate, and a three-input OR-NAND as well as a static RAM bit cell. SEU immunity is obtained by constructing each logic element with a redundant set of inputs and using two copies of each such logic element to provide redundant outputs. The design of a logic element is such that when the redundant inputs agree (i.e., each has the same logic value), then the output of the logic element implements the logic function. However, when any pair of redundant inputs disagree, then the output of the logic element is disconnected (tri-state), which preserves the previous output value. SEU events only affect one of the logic elements in the pair, and this upset can not propagate through other logic elements because of the tri-state function.

1 . A single event upset (SEU) immune logic function circuit comprising: 
 a plurality of logic sub-circuits wherein each logic sub-circuit is comprised of redundant inputs, such that 
 when the redundant inputs are not the same the output becomes tri-state; and when the redundant inputs are the same the output is driven in accordance with the logic function.  
   
     
     
         2 . The SEU immune logic circuit of  claim 1  wherein said logic function circuit is implemented using a complementary metal-oxide semi-conductor (CMOS) process.  
     
     
         3 . A single event upset (SEU) immune inverter circuit comprising: 
 a primary p-channel CMOS transistor, T 1 , and a redundant p-channel CMOS transistor, T 2 ; and    a primary n-channel CMOS transistor, T 3 , and a redundant n-channel CMOS transistor, T 4 ;    wherein each transistor is comprised of a gate, a source, and a drain and said transistors are coupled such that,    a primary input is coupled with the gate of T 1  and the gate of T 3 ;    a redundant input is coupled with the gate of T 2  and the gate of T 4 ;    the source of T 1  is coupled with a power supply;    the drain of T 1  is coupled with the source of T 2 ;    the drain of T 2  is coupled with an output, Y;    the drain of T 3  is coupled with the output, Y;    the source of T 3  is coupled with the drain of T 4 ; and    the source of T 4  is coupled with ground.    
     
     
         4 . A single event upset (SEU) immune memory cell comprised of: 
 a series of cross coupled inverter circuits; and    a set of drive transistors having multiple I/O pins that drive the SEU inverter circuits, wherein each inverter circuit is an SEU immune inverter circuit comprised of:    a primary p-channel CMOS transistor, T 1 , and a redundant p-channel CMOS transistor, T 2 ; and    a primary n-channel CMOS transistor, T 3 , and a redundant n-channel CMOS transistor, T 4 ;    wherein each transistor is comprised of a gate, a source, and a drain and said transistors are coupled such that,    a primary input is coupled with the gate of T 1  and the gate of T 3 ;    a redundant input is coupled with the gate of T 2  and the gate of T 4 ;    the source of T 1  is coupled with a power supply;    the drain of T 1  is coupled with the source of T 2 ;    the drain of T 2  is coupled with an output, Y;    the drain of T 3  is coupled with the output, Y;    the source of T 3  is coupled with the drain of T 4 ; and    the source of T 4  is coupled with ground.    
     
     
         5 . A single event upset (SEU) immune two-input NOR circuit comprising: 
 primary p-channel CMOS transistors, T 1  and T 3 , and redundant p-channel CMOS transistors, T 2  and T 4 ; and    primary n-channel CMOS transistors, T 6  and T 8 , and a redundant n-channel CMOS transistors, T 5  and T 7 ;    wherein each transistor is comprised of a gate, a source, and a drain and said transistors are coupled such that,    a first primary input, A 1 , is coupled with the gate of T 1  and the gate of T 8 ;    a first redundant input, A 2 , is coupled with the gate of T 2  and the gate of T 7 ;    a second primary input, B 1 , is coupled with the gate of T 3  and the gate of T 6 ;    a second redundant input, B 2 , is coupled with the gate of T 4  and the gate of T 5 ;    the source of T 1  is coupled with a power supply;    the drain of T 1  is coupled with the source of T 2 ;    the drain of T 2  is coupled with the source of T 3 ;    the drain of T 3  is coupled with the source of T 4 ;    the drain of T 4  is coupled with an output, Y;    the drain of T 5  is coupled with the output, Y;    the source of T 5  is coupled with the drain of T 6 ;    the source of T 6  is coupled with ground;    the drain of T 7  is coupled with the output, Y;    the source of T 7  is coupled with the drain of T 8 ; and    the source of T 8  is coupled with ground.    
     
     
         6 . A single event upset (SEU) immune two-input NAND circuit comprising: 
 primary p-channel CMOS transistors, T 1  and T 3 , and redundant p-channel CMOS transistors, T 2  and T 4 ; and    primary n-channel CMOS transistors, T 6  and T 8 , and a redundant n-channel CMOS transistors, T 5  and T 7 ;    wherein each transistor is comprised of a gate, a source, and a drain and said transistors are coupled such that,    a first primary input, A 1 , is coupled with the gate of T 1  and the gate of T 8 ;    a first redundant input, A 2 , is coupled with the gate of T 2  and the gate of T 7 ;    a second primary input, B 1 , is coupled with the gate of T 3  and the gate of T 6 ;    a second redundant input, B 2 , is coupled with the gate of T 4  and the gate of T 5 ;    the source of T 1  is coupled with a power supply;    the drain of T 1  is coupled with the source of T 2 ;    the drain of T 2  is coupled with an output, Y;    the source of T 3  is coupled with the power supply;    the drain of T 3  is coupled with the source of T 4 ;    the drain of T 4  is coupled with the output, Y;    the drain of T 5  is coupled with the output, Y;    the source of T 5  is coupled with the drain of T 6 ;    the source of T 6  is coupled with the drain of T 7 ;    the source of T 7  is coupled with the drain of T 8 ; and    the source of T 8  is coupled with ground.    
     
     
         7 . A single event upset (SEU) immune three-input AND-NOR circuit comprising: 
 primary p-channel CMOS transistors, T 1 , T 3  and T 5 , and redundant p-channel CMOS transistors, T 2 , T 4  and T 6 ; and    primary n-channel CMOS transistors, T 8 , T 10  and T 12 , and redundant n-channel CMOS transistors, T 7 , T 9  and T 11 ;    wherein each transistor is comprised of a gate, a source, and a drain and said transistors are coupled such that,    a first primary input, A 1 , is coupled with the gate of T 1  and the gate of T 12 ;    a first redundant input, A 2 , is coupled with the gate of T 2  and the gate of T 11 ;    a second primary input, B 1 , is coupled with the gate of T 3  and the gate of T 10 ;    a second redundant input, B 2 , is coupled with the gate of T 4  and the gate of T 9 ;    a third primary input, C 1 , is coupled with the gate of T 5  and the gate of T 8 ;    a third redundant input, C 2 , is coupled with the gate of T 6  and the gate of T 7 ;    the source of T 1  is coupled with a power supply;    the drain of T 1  is coupled with the source of T 2 ;    the drain of T 2  is coupled with the drain of T 4 ;    the source of T 3  is coupled with the power supply;    the drain of T 3  is coupled with the source of T 4 ;    the drain of T 4  is coupled with the drain of T 2 ;    the source of T 5  is coupled with the drain of T 2  and the drain of T 4 ;    the drain of T 5  is coupled with the source of T 6 ;    the drain of T 6  is coupled with an output, Y;    the drain of T 7  is coupled with the output, Y;    the source of T 7  is coupled with the drain of T 8 ;    the source of T 8  is coupled with ground;    the drain of T 9  is coupled with the output, Y;    the source of T 9  is coupled with the drain of T 10 ;    the source of T 10  is coupled with the drain of T 11 ;    the source of T 11  is coupled with the drain of T 12 ; and    the source of T 12  is coupled with ground.    
     
     
         8 . A single event upset (SEU) immune three-input OR-NAND circuit comprising: 
 primary p-channel CMOS transistors, T 1 , T 3  and T 5 , and redundant p-channel CMOS transistors, T 2 , T 4  and T 6 ; and    primary n-channel CMOS transistors, T 8 , T 10  and T 12 , and redundant n-channel CMOS transistors, T 7 , T 9  and T 11 ;    wherein each transistor is comprised of a gate, a source, and a drain and said transistors are coupled such that,    a first primary input, A 1 , is coupled with the gate of T 1  and the gate of T 12 ;    a first redundant input, A 2 , is coupled with the gate of T 2  and the gate of T 11 ;    a second primary input, B 1 , is coupled with the gate of T 3  and the gate of T 10 ;    a second redundant input, B 2 , is coupled with the gate of T 4  and the gate of T 9 ;    a third primary input, C 1 , is coupled with the gate of T 5  and the gate of T 8 ;    a third redundant input, C 2 , is coupled with the gate of T 6  and the gate of T 7 ;    the source of T 1  is coupled with a power supply;    the drain of T 1  is coupled with the source of T 2 ;    the drain of T 2  is coupled with the source of T 3 ;    the drain of T 3  is coupled with the source of T 4 ;    the drain of T 4  is coupled with an output, Y;    the source of T 5  is coupled with the power supply;    the drain of T 5  is coupled with the source of T 6 ;    the drain of T 6  is coupled with the output, Y;    the drain of T 7  is coupled with the output, Y;    the source of T 7  is coupled with the drain of T 8 ;    the source of T 5  is coupled with drain of T 11 ;    the drain of T 9  is coupled with the drain of T 11 ;    the source of T 9  is coupled with the drain of t 10 ;    the source of T 10  is coupled with ground;    the drain of T 11  is coupled with the source of T 8  and the drain of T 9 ; and    the source of T 11  is coupled with drain of T 12 ; and    the source of T 12  is coupled with ground.