Die architecture accommodating high-speed semiconductor devices

Abstract

In a semiconductor memory device, a die architecture is provided that arranges memory arrays into a long, narrow configuration. Bond pads may then be placed along a long side of a correspondingly shaped die. As a result, this architecture is compatible with short lead frame “fingers” for use with wide data busses as part of high speed, multiple band memory integrated circuits.

What is claimed is:  
     
         1 . A method of allowing generally synchronous communication between an external device and memory sub-arrays on a die, comprising: 
 arranging said memory sub-arrays generally along a dimension of said external device; and    accommodatingly shaping said die in relation to said memory sub-arrays.    
     
     
         2 . The method in  claim 1 , further comprising: 
 providing a plurality of bond pads on said die;    coupling each sub-array to a bond pad of said plurality of bond pads; and    arranging said plurality of bond pads on said die generally along said dimension of said external device.    
     
     
         3 . A method of providing for electrical communication between an external device and memory banks comprised of sub-arrays on a die, comprising: 
 cooperatively configuring dimensions of said die in relation to said external device; and generally conformably arranging said memory banks within said dimensions of said die, further comprising: 
 discontiguously arranging at least one sub-array in at least one memory bank in relation to other sub-arrays of said one memory bank.  
   
     
     
         4 . A method of conforming a die for operation with a lead frame having lead fingers of generally equal length, comprising: 
 providing a first memory bank comprising a first plurality of sub-arrays;    providing a second memory bank comprising a second plurality of sub-arrays, 
 wherein said second plurality of sub-arrays is equal in number to said first plurality of sub-arrays;  
   providing a plurality of access pads on said die, wherein said plurality of access pads is equal in number to said first plurality of sub-arrays;    associating each access pad of said plurality of access pads with one sub-array from said first plurality of sub-arrays and one sub-array from said second plurality of sub-arrays;    arranging one sub-array of every sub-array from said first plurality of sub-arrays and an associated sub-array from said second plurality of sub-arrays near a lead finger; and    placing each access pad between a lead finger and associated sub-arrays from said first and second plurality of sub-arrays.    
     
     
         5 . The method in  claim 4 , further comprising placing at least one unassociated sub-array between one access pad and said associated sub-arrays.  
     
     
         6 . The method in  claim 5 , further comprising placing at most three unassociated sub-arrays between one access pad and associated sub-arrays from said first plurality of sub-arrays and said second plurality of sub-arrays.  
     
     
         7 . A method of configuring a die having a length and a depth, comprising: 
 providing a plurality of sub-arrays on said die, said plurality of sub-arrays comprising a first sub-array group and a second sub-array group;    placing said first sub-array group generally entirely along said length of said die;    placing said second sub-array group along said depth of said die;    providing a plurality of bond pads on said die generally entirely along said length of said die;    associating proximate sub-arrays of said plurality of sub-arrays with a particular bond pad of said plurality of bond pads.    
     
     
         8 . The method in  claim 7 , further comprising placing bond pads next to associated sub-arrays.  
     
     
         9 . A method of constructing a memory circuit, comprising: 
 providing a plurality of memory banks on a die, further comprising providing a plurality of sub-arrays for each memory bank;    providing a plurality of access pads on said die;    electrically associating each access pad of said plurality of access pads with one sub-array from each memory bank;    providing a physical separation of a first group of sub-arrays from a second group of sub-arrays within each memory bank; and    physically associating sub-arrays that are commonly electrically associated with an access pad.    
     
     
         10 . The method in  claim 9 , wherein physically associating sub-arrays further comprises establishing a number of sub-array associations equal in number to said plurality of memory banks.  
     
     
         11 . The method in  claim 10 , further comprising providing a plurality of bond pads on one side of said die, wherein said plurality of access pads is a subset of said plurality of bond pads.  
     
     
         12 . The method in  claim 11 , further comprising physically orienting said plurality of sub-arrays in each memory bank perpendicular to said one side of said die.  
     
     
         13 . The method in  claim 12 , wherein physically associating said sub-arrays further comprises configuring one-dimensional groupings.  
     
     
         14 . The method in  claim 12 , wherein physically associating said sub-arrays further comprises configuring two-dimensional groupings.  
     
     
         15 . A method of configuring a die, comprising: 
 providing a plurality of memory sub-arrays on said die;    defining at least one memory bank from said memory sub-arrays;    providing row decoder circuitry and column decoder circuitry for said memory bank; and    fragmenting said row decoder circuitry into a number of portions exceeding a number of defined memory banks.    
     
     
         16 . The method in  claim 15 , wherein fragmenting said row decoder circuitry further comprises defining a plurality of parallel axes with portions of said row decoder circuitry.  
     
     
         17 . The method in  claim 16 , further comprising fragmenting said column decoder circuitry.  
     
     
         18 . The method in  claim 17 , wherein defining at least one memory bank further comprises defining a plurality of memory banks from said plurality of memory sub-arrays; and wherein said method further comprises proximately positioning corresponding memory sub-arrays of each memory bank.  
     
     
         19 . The method in  claim 18 , further comprising locationally separating some memory sub-arrays within a memory bank.  
     
     
         20 . A circuit configured to operate with an external device, comprising: 
 a die having a device accommodatable dimension;    a first memory bank on said die further comprising a first sub-array and a second sub-array;    a second memory bank on said die further comprising a third sub-array and a fourth sub-array;    a first sub-array arrangement further comprising said first sub-array and said third sub-array;    a second sub-array arrangement further comprising said second sub-array and said fourth sub-array and aligned with said first sub-array arrangement along said device accommodatable dimension;    a first access pad coupled to said first sub-array arrangement; and    a second access pad coupled to said second sub-array arrangement and aligned with said first access pad along said device accommodatable dimension.    
     
     
         21 . The circuit in  claim 20 , wherein said first sub-array arrangement is next to said second sub-array arrangement; said third sub-array is next to said fourth sub-array; and said first sub-array is isolated from said second sub-array.  
     
     
         22 . The circuit in  claim 20 , wherein said first sub-array arrangement is next to said second sub-array arrangement; said third sub-array is next to said fourth sub-array; and said third and fourth sub-arrays are interposed between said first and second sub-arrays.  
     
     
         23 . A memory array, comprising: 
 a plurality of memory banks on a die, wherein each memory bank further comprises a plurality of sub-arrays and a first portion of said plurality of sub-arrays for each memory bank is physically isolated from a second portion of said plurality of sub-arrays; and    a plurality of access pads on one side of said die, wherein each access pad is coupled to one sub-array from every memory bank; and wherein a sub-array coupled to an access pad is generally proximate to other sub-arrays coupled to said access pad, all of said sub-arrays coupled to one access pad defining a particular sub-array group.    
     
     
         24 . The memory array of  claim 23 , wherein said plurality of sub-arrays have an orientation parallel with said one side of said die.  
     
     
         25 . The memory array of  claim 24 , wherein each particular sub-array group comprises at least two sub-arrays aligned along said one side of said die.  
     
     
         26 . The memory array of  claim 25 , wherein a sub-array of one sub-array group is in the same bank as a contiguous sub-array in another sub-array group.  
     
     
         27 . The memory array of  claim 25 , wherein a particular sub-array group is aligned perpendicular to said one side of said die.  
     
     
         28 . A memory system, comprising: 
 a die;    a plurality of memory banks on said die;    a plurality of bond pads on one side of said die; and    column select circuitry on said die defining an axis generally parallel to said plurality of bond pads and passing through every memory bank of said plurality of memory banks.    
     
     
         29 . The memory system of  claim 28 , further comprising column decoder circuitry coupled to said column select circuitry and oriented generally perpendicular to said column select circuitry.  
     
     
         30 . A packaged integrated circuit configured to communicate with an external device having a plurality of data terminals, comprising: 
 a lead frame having a plurality of conductive leads generally corresponding to said plurality of data terminals;    a die attached to said lead frame and further comprising: 
 a plurality of discontiguous memory banks on said die generally conformal to dimensions of said die, and  
 a plurality of bond pads generally corresponding to said plurality of conductive leads and coupled to said plurality of discontiguous memory banks; and  
 a plurality of bond wires connecting said plurality of bond pads to said plurality of conductive leads.  
   
     
     
         31 . The packaged integrated circuit in  claim 30 , wherein said plurality of discontiguous memory banks further comprises a plurality of partially discontiguous memory banks.  
     
     
         32 . The packaged integrated circuit in  claim 31 , said plurality of partially discontiguous memory banks further comprises a plurality of intervally continuous memory banks.  
     
     
         33 . The packaged integrated circuit in  claim 32 , wherein said plurality of intervally continuous memory banks comprises two sub-arrays from one memory bank physically separated by at least one sub-array of at least one other memory bank.  
     
     
         34 . The packaged integrated circuit in  claim 30 , wherein said plurality of discontiguous memory banks comprises two sequential sub-arrays from one memory bank physically separated by at least one sub-array from at least one other memory bank.  
     
     
         35 . The packaged integrated circuit in  claim 30 , wherein said plurality of discontiguous memory banks comprises two sub-arrays from one memory bank physically separated by one sub-array from every other memory bank.