Semiconductor device with heavily doped shallow region and process for fabricating the same

Abstract

A process for fabricating semiconductor devices, comprises forming a surface film on the surface of a semiconductor substrate. The semiconductor substrate is doped with dopant through the surface film to form a dopant distribution layer. The doped surface film is removed, and then anneal is done to accomplish desired dopant profile of the box type.

What is claimed is:  
     
         1 . A semiconductor device, comprising: 
 a semiconductor substrate having a collector region doped with a first dopant; and    a base region formed into the substrate and has a thickness, in depth direction, that is less than or equal to 0.05 μm, the base region being doped with a second dopant and having a dopant profile,    the dopant profile having dopant concentrations whose maximum level (N) is greater than 3.0×10 18 /cm 3  and less than 5.0×10 18 /cm 3 ,    over at least 60% of the thickness of the base region, the difference between the dopant concentrations and the maximum level (N) falling in 10% in a of the maximum level (N),    the thickness of the base region being the depth of a range where the dopant concentrations are greater than or equal to a dopant concentration of the first dopant of the collector region.    
     
     
         2 . A semiconductor device, comprising: 
 a semiconductor substrate; and    a base region formed into the substrate and has a thickness, in depth direction, that is less than or equal to 0.05 μm, the base region being doped with a second dopant and having a dopant profile,    the dopant profile having dopant concentrations whose maximum level (N) is greater than 3.0×10 15 /cm 3  and less than 5.0×10 18 /cm 3 ,    over at least 60% of the thickness of the base region, the difference between the dopant concentrations and the maximum level (N) falling in 10% of the maximum level (N),    the thickness of the base region being the depth of a range where the dopant concentrations are greater than or equal to a dopant concentration value of 2×10 17 /cm  3 .    
     
     
         3 . A process for fabricating semiconductor devices, comprising: 
 forming a surface film on the surface of a semiconductor substrate;    doping the semiconductor substrate with dopant through the surface film to form a dopant distribution layer;    removing the surface film doped with the dopant; and    annealing the semiconductor substrate after the removing of the surface film.    
     
     
         4 . The process as claimed in  claim 3 , further comprising; 
 annealing the semiconductor substrate with the surface film before the removing of the surf ace film.    
     
     
         5 . The process as claimed in  claim 3 , 
 wherein the semiconductor substrate is formed with a region adjacent to the dopant distribution layer;    wherein the thickness in the depth direction of the dopant distribution layer is less than 0.07 μm; and    wherein the thickness of the dopant distribution layer is the depth of a range where tho dopant concentrations are greater than or equal to a dopant concentration of the adjacent region within the semiconductor substrate.    
     
     
         6 . The process as claimed in  claim 4 , 
 Wherein the semiconductor substrate Is formed with a region adjacent to the dopant distribution layer;    wherein the thickness in the depth direction of the dopant distribution layer is less than 0.07 μm; and    wherein the thickness of the dopant distribution layer is the depth of a range where the dopant concentrations are greater than or equal to a dopant concentration of the adjacent region within the semiconductor substrate.    
     
     
         7 . The process as claimed in  claim 3 , 
 wherein the thickness in the depth direction of the dopant distribution layer is less than 0.07 μm; and    wherein the thickness of the dopant distribution layer is the depth of a range where the dopant concentrations are greater than or equal to a dopant concentration value of 2×10 17 /cm 3 .    
     
     
         8 . The process as claimed in  claim 4 , 
 wherein the thickness in the depth direction of the dopant distribution layer is less than 0.07 μm; and    wherein the thickness of the dopant distribution layer is the depth of a range where the dopant concentrations are greater than or equal to a dopant concentration value of 2×10 17 /cm 3 .    
     
     
         9 . The process as claimed in  claim 3 , 
 wherein the dopant distribution layer has a dopant profile, the dopant profile having dopant concentrations whose maximum level (N) is greater than 3.0×10 18 /cm 3  and less than 5.0×10 18 /cm 3 ,    over at least 70% of the thickness of the dopant distribution layer, the difference between the dopant concentrations and the maximum level (N) falling in 10% of the maximum level (N).    
     
     
         10 . The process as claimed in  claim 4 , 
 wherein the dopant distribution layer has a dopant profile, the dopant profile having dopant concentrations whose maximum level (N) is greater than 3.0×10 18 /cm 3  and less than 5.0×10 18 /cm 3 ,    over at least 70% of the thickness of the dopant distribution layer, the difference between the dopant concentrations and the maximum level (N) falling in 10% of the maximum level (N).    
     
     
         11 . The process as claimed in  claim 5 , 
 wherein the dopant distribution layer has a dopant profile, the dopant profile having dopant concentrations whose maximum level (N) is greater than 3.0×10 18 /cm  3  and less than 5.0×10 18 /cm 3 ,    over at least 70% of the thickness of the dopant distribution layer, the difference between the dopant concentrations and the maximum level (N) falling in 10% of the maximum level (N).    
     
     
         12 . The process as claimed in  claim 6 , 
 wherein the dopant distribution layer has a dopant profile, the dopant profile having dopant concentrations whose maximum level (N) is greater than 3.0×10 18 /cm 3  and less than 5.0×10 18 /cm 3 ,    over at least 70% of the thickness of the dopant distribution layer, the difference between the dopant concentrations and the maximum level (N) falling in 10% of the maximum level (N).    
     
     
         13 . The process as claimed in  claim 7 . 
 wherein the dopant distribution layer has a dopant profile, the dopant profile having dopant concentrations whose maximum level (N) is greater than 3.0×10 18 /cm 3  and less than 5.0×10 18 /cm 3 ,    over at least 70% of the thickness of the dopant distribution layer, the difference between the dopant concentrations and the maximum level (N) falling in 10% of the maximum level (N).    
     
     
         14 . The process as claimed in  claim 8 . 
 wherein the dopant distribution layer has a dopant profile, the dopant profile having dopant concentrations whose maximum level (N) is greater than 3.0×10 18 /cm 3  and less than 5.0×10 18 /cm 3 ,    over at least 70% of the thickness of the dopant distribution layer, the difference between the dopant concentrations and the maximum level (N) falling in 10% of the maximum level (N).    
     
     
         15 . The process as claimed in  claim 3 , wherein the annealing step is done within inert gas atmosphere.  
     
     
         16 . The process as claimed in  claim 4 , wherein at least one of the annealing steps is done within inert gas atmosphere.  
     
     
         17 . The process as claimed in  claim 3 , wherein annealing temperature of the annealing step is higher than or equal to 800° C. but lower than or equal to 950° C.  
     
     
         18 . The process as claimed in  claim 4 , wherein annealing temperature of at least one of the annealing steps is higher than or equal to 800° C. but lower than or equal to 950° C.  
     
     
         19 . The process as claimed in  claim 3 , wherein the annealing step is done for a period of time longer than or equal to 5 seconds but shorter than or equal to 20 minutes.  
     
     
         20 . The process as claimed in  claim 4 , wherein at least one of the annealing steps is done for a period of time longer than or equal to 5 seconds but shorter than or equal to 20 minutes.  
     
     
         21 . The process as claimed in  claim 3 , wherein the surface film is made of an insulating layer.  
     
     
         22 . The process as claimed in  claim 21 , wherein the insulating layer is made of one of silicon dioxide and silicon nitride,  
     
     
         23 . The process as claimed in  claim 3 , wherein an intrinsic base region of a bipolar transistor is formed from the dopant distribution layer.  
     
     
         24 . The process as claimed in  claim 3 , wherein the annealing step is done by a lamp anneal within nitrogen atmosphere at annealing temperature of from 850° C. to 950° C. for 10 seconds to 60 seconds.  
     
     
         25 . The process as claimed in  claim 3 , wherein the annealing step is done by a furnace anneal within nitrogen atmosphere at annealing temperature of from 800° C. to 900° C. for 5 minutes to 10 minutes.  
     
     
         26 . A process For fabricating semiconductor devices, comprising; 
 forming a surface film on the surface of a semiconductor substrate;    doping, by ion implantation, the semiconductor substrate with dopant through the surface film to form a dopant distribution layer:    removing the surface film doped with the dopant:    annealing the semiconductor with the surface film by a lamp anneal within nitrogen atmosphere at annealing temperature of from 850° C. to 950° for 10 seconds to 60 seconds;    removing the surface film doped with the dopant;    annealing the semiconductor substrate after the removing of the surface film by a lamp anneal within nitrogen atmosphere at annealing temperature of from 850° C. to 950° for 10 seconds to 60 seconds.    
     
     
         27 . A process for fabricating semiconductor devices, comprising; 
 forming a surface film on the surface of a semiconductor substrate;    doping, by ion implantation, the semiconductor substrate with dopant through the surface film to form a dopant distribution layer;    removing the surface film doped with the dopant;    annealing the semiconductor with the surface film by a lamp anneal within nitrogen atmosphere at annealing temperature of from 850° C. to 950° for 10 seconds to 60 seconds;    removing the surface film doped with the dopant;    annealing the semiconductor substrate after the removing of the surface film by a furnace anneal within nitrogen atmosphere at annealing temperature of from 800° C. to 900° for 5 minutes to 10 minutes.