Diffusion resistor/capacitor (drc) non-aligned mosfet structure

Abstract

A structure and process for making a non-aligned MOSFET structure for ESD protection using resistor wells as the diffusions and adjustable capacitors. The present invention compensates the shallow extension region without the need for additional masks. The source/drain doping is less than that of a normal MOSFET but extends deeper into the silicon since the present invention uses a resistor well as the source/drain. The deeper emitter/collector increases the second trigger current of the NFET when used as an ESD protection device.

Thus, having described the invention, what is claimed is:  
     
         1 . A non-self aligned MOSFET transistor for ESD protection comprising: 
 (a) a substrate having a source diffusion region and a drain diffusion region;    (b) a first and second resistor well implant;    (c) said first resistor well implanted into said source diffusion region on said substrate forming a first resistor well having a junction depth extending into said substrate;    (d) said second resistor well implanted into said drain diffusion region on said substrate forming a second resistor well having a junction depth extending into said substrate;    (e) said first resistor well and second resistor well being spaced apart to define a channel region there between;    (f) said channel region connecting said first and second resistor wells;    (g) a gate oxide layer overlying said channel; and    (h) a gate electrode overlying said oxide layer.    
     
     
         2 . The MOSFET structure of  claim 1 , wherein said gate oxide layer and gate electrode form a gate.  
     
     
         3 . The MOSFET structure of  claim 1 , further comprising: 
 (i) an N-extension mask placed over said gate electrode and implanted into said gate.    
     
     
         4 . The MOSFET structure of  claim 1 , wherein the gate oxide layer is silicon oxide.  
     
     
         5 . The MOSFET structure of  claim 1 , wherein the gate electrode is polysilicon.  
     
     
         6 . The MOSFET structure of  claim 1 , wherein said gate oxide layer and gate electrode extend on top of and overlap said first and second resistor wells forming a first and second overlap region.  
     
     
         7 . The MOSFET structure of  claim 6 , wherein the amount of the overlap of the first and second overlap regions is variable.  
     
     
         8 . The MOSFET structure of  claim 1 , wherein the junction depth of said first and second resistor wells is variable.  
     
     
         9 . The MOSFET structure of  claim 8 , wherein a silicide blocking mask is deposited above said first and second resistor wells thereby inhibiting the formation of silicide and deepening the junction depths of the first and second resistor wells.  
     
     
         10 . The MOSFET structure of  claim 1 , wherein the junction depths of the first and second resistor well extend to approximately 0.40 um.  
     
     
         11 . The MOSFET structure of  claim 1 , further comprising a third resistor tub overlying and embedded in said second resistor well to form a resistor ballasted NFET.  
     
     
         12 . The MOSFET structure of  claim 7 , wherein a variable capacitor is formed between said gate electrode and drain diffusion region by the overlap in the second overlap region.  
     
     
         13 . The MOSFET structure of  claim 12 , wherein a variable resistor-capacitor controlled network is formed on the gate electrode of the MOSFET by said variable capacitor in combination with said first resistor well.  
     
     
         14 . A method of manufacturing a non-self aligned MOSFET transistor for ESD protection comprising the steps of: 
 a) providing a substrate having a source diffusion region and a drain diffusion region;    b) implanting a first resistor tub into said source diffusion region forming a first resistor well having a first junction depth;    c) implanting a second resistor tub into said drain diffusion region forming a second resistor well having a second junction depth, said first resistor well separated from said second resistor well by a channel region there between;    d) depositing a gate oxide layer and gate electrode to form a gate.    
     
     
         15 . The method of  claim 14 , wherein in step (d), the gate oxide layer is silicon oxide and said gate electrode is polysilicon.  
     
     
         16 . A method of  claim 14 , wherein in step (d) the gate oxide layer is extended onto and overlaps said first and second resistor wells to define a first and second overlap region.  
     
     
         17 . The method of  claim 14 , further comprising extending the first and second junction depth to approximately 0.40 um.  
     
     
         18 . The method of  claim 14  further comprising the steps of (e) forming an n-extension mask over the top of the gate electrode and implanted said mask into said gate.  
     
     
         19 . The method of  claim 14 , further comprising the step, between steps (c) and (d), of depositing a silicide blocking mask over the first and second resistor wells, said blocking mask inhibiting the formation of silicide and thereby deepening the junction depths of the first and second resistor wells.  
     
     
         20 . The method of  claim 14 , further comprising the step of overlying and embedding a third resistor tub in the second resistor well to form a resistor ballasted NFET.