Chemical mechanical polishing of dielectric materials

Abstract

A semiconductor wafer has, an underlying dielectric layer with non-planarity features at its surface due to damascene topology, and a successive dielectric layer that is without damascene topology overlying the first dielectric layer, the successive dielectric layer having a smooth polished planar surface that minimizes cumulative non-planarity. The surface is polished by chemical-mechanical planarization with a reactive liquid borne by an aqueous polishing fluid applied at an interface of the successive dielectric layer and a polishing pad.

What is claimed is:  
     
         1 . A method for minimizing cumulative non-planarity of a semiconductor wafer comprising the steps of; 
 applying a successive dielectric layer that is without damascene topology over both an underlying dielectric layer and a topology of non-planarity features on the underlying dielectric layer, the successive dielectric layer having a sufficient thickness to become reduced in thickness upon being polished, and polishing the successive dielectric layer to provide on the successive dielectric layer a smooth planar polished surface that minimizes non-planarity due to the topology of non-planarity features on the underlying dielectric layer.    
     
     
         2 . The method as recited in  claim 1 , further comprising the step of; polishing the semiconductor wafer prior to applying the successive dielectric layer, to remove excess metallization from the surface of the underlying dielectric layer, leaving the underlying dielectric layer with the topology of non-planarity features.  
     
     
         3 . A semiconductor wafer comprises, an underlying dielectric layer with non-planarity features at its surface provided by damascene topology, and a successive dielectric layer that is without damascene topology overlying the underlying dielectric layer, the successive dielectric layer having a smooth polished planar surface that minimizes cumulative non-planarity.  
     
     
         4 . The semiconductor wafer according to  claim 3 , and further comprising: the underlying dielectric layer having non-planarity features at its surface due to dished metal in trenches in the underlying dielectric layer.  
     
     
         5 . The semiconductor wafer according to  claim 3 , and further comprising: the underlying dielectric layer having non-planarity features at its surface due to recessed erosion of the underlying dielectric layer.  
     
     
         6 . A kit of parts having materials for application to a surface of a semiconductor wafer, comprises: a low K dielectric material, and a reactive liquid for soluble dissolution of the surface of the low K dielectric during CMP polishing using the reactive liquid in a polishing fluid during CMP polishing to provide a smooth planar polished surface on the low K dielectric material.  
     
     
         7 . A kit of parts having materials for polishing a surface of a semiconductor wafer, comprises: a low K dielectric material and a reactive liquid for soluble dissolution of the surface of the low K dielectric material during CMP polishing to be used as a reactive liquid borne by a polishing fluid for dissolution of the low K dielectric material during CMP polishing of the low K dielectric material to provide a smooth planar polished surface on the low K dielectric material.