Semiconductor package having an insulating region on an edge of a chip to prevent shorts

Abstract

A semiconductor package and a manufacturing method prevent electrical shorts that otherwise result from bonding wires contacting the edge of a semiconductor chip. An insulating region at the edge of a semiconductor chip prevents the shorts. One method for forming the insulating region leaves a polyimide layer on the scribe area of a wafer and cuts through the polyimide layer. To avoid chipping, the cutting uses a fine grit blade and a slow cutting rate. An alternative process removes the polyimide from the scribe area and forms the insulating region on the edge of the semiconductor chip. A potting method can deposit the insulating region on a semiconductor chip after cutting a wafer and after attaching a separated chip to a substrate. Alternatively, plotting or printing can apply insulating material on the wafer. A cutting process then cuts through the insulating material and the wafer and leaves insulating regions on each separated chip. A groove can be formed in the scribe area and then filled with insulating material before cutting along the groove. As a result, the insulating material from inside the groove extends onto the sides of the separated semiconductor chips. If the groove is formed before backside grinding of the wafer, the insulating region can cover the side of a chip. The insulating material is typically an epoxy type resin that can be cut without chipping.

What is claimed is:  
     
         1 . A semiconductor package comprising: 
 a semiconductor chip including a silicon substrate having an active area, a plurality of pads in a center portion of the active area, and a polyimide layer overlying the active area and extending to an edge of the semiconductor chip;    a substrate on which the semiconductor chip is attached; and    a bonding wire electrically connecting one of the pads of the semiconductor chip to the substrate, wherein the bonding wire contacts the polyimide layer at the edge of the semiconductor chip, whereby the polyimide layer prevents an electrical short between the bonding wire and the silicon substrate.    
     
     
         2 . The semiconductor package of  claim 1 , further comprising: 
 a resin encapsulation portion for encapsulating the semiconductor chip and the bonding wire at an upper surface of the substrate; and    a plurality of external terminals formed on a lower surface of the substrate and electrically connected with the semiconductor chip.    
     
     
         3 . A semiconductor package comprising: 
 a semiconductor chip including a silicon substrate having an active area, a plurality of pads in a center portion of the active area, and an insulation layer formed along an edge of the silicon substrate;    a substrate on which the semiconductor chip is attached; and    a bonding wire electrically connecting one of the pads of the semiconductor chip to the substrate, wherein the bonding wire contacts the insulation layer at the edge of the semiconductor chip, whereby the insulation layer prevents an electrical short between the bonding wire and the silicon substrate.    
     
     
         4 . The semiconductor package according to  claim 3 , wherein the semiconductor chip further comprises: 
 a non-active layer formed on the active area except for the pads; and    a polyimide layer formed on the non-active except for the pads and the edge of semiconductor chip.    
     
     
         5 . The semiconductor package according to  claim 4 , wherein the insulation layer is formed on the edge of the active surface of the semiconductor chip, where the polyimide layer is absent.  
     
     
         6 . The semiconductor package according to  claim 5 , wherein the insulation layer extends past the edge of the semiconductor chip and onto a portion of a side surface of the semiconductor chip.  
     
     
         7 . The semiconductor package according to  claim 3 , wherein the insulation layer is a plastic resin of an epoxy type.  
     
     
         8 . The semiconductor package of  claim 3 , further comprising: 
 a resin encapsulation portion for encapsulating the semiconductor chip and the bonding wire at an upper surface of the substrate; and    a plurality of external terminals formed on a lower surface of the substrate and electrically connected with the semiconductor chip.