Flash EEPROM cell and method of manufacturing the same

Abstract

The invention relates to a flash EEPROM cell and method of manufacturing the same. The method of manufacturing a flash EEPROM cell includes sequentially forming a tunnel oxide film, a polysilicon layer for a floating gate and a hard mask layer on a semiconductor substrate; patterning the hard mask layer and then forming a hard mask layer spacer at the etching side of the patterned hard mask layer; removing the exposed portion of the ploysilicon layer for the floating gate by etching process using the patterned hard mask layer and the hard mask layer spacer as etching masks thus to form first and second patterns that are separated in two; removing the patterned hard mask layer and the hard mask layer spacer and then depositing a dielectric film and a polysilicon layer for a floating gate on the entire structure, thus forming a first floating gate, a second floating gate and a control gate by self-aligned etching process; and forming a drain junction and a source junction by cell source/drain ion implantation process. Thus, the present invention can prevent lower of the quality of the tunnel oxide film and thus increase the coupling ratio.

What is claimed is:  
     
         1 . A flash EEPROM cell, comprising: 
 first and second floating gates, that are different in size and separated in two, formed to be electrically separated from a semiconductor substrate by a tunnel oxide film;    control gate formed to be electrically separated from said first and second floating gates by a dielectric film;    drain junction formed on said semiconductor substrate at the side of said first floating gate; and    source junction formed on said semiconductor substrate at the side of said second floating gate.    
     
     
         2 . The flash EEPROM cell according to  claim 1 , wherein the ratio of the size of the first floating gate to the second floating gate is {fraction (1/3)} to less than  1 .  
     
     
         3 . A flash EEPROM cell comprising: 
 a semiconductor substrate;    spaced apart drain and source junctions formed in the semiconductor substrate;    spaced apart first and second portions of a first film formed above the semiconductor substrate, the first portion of the first film at least partially overlapping one of the drain and source junctions and the second portion of the first film at least partially overlapping the other of the drain and source junctions;    a first floating gate formed above the first portion of the first film and a second floating gate formed above the second portion of the first film, the first and second floating gates being spaced apart from one another by a gap and having opposing sidewalls;    a dielectic film formed above the first and second floating gates and also covering the opposing sidewalls of the first and second floating gates;    a control gate formed on the dielectric film, the control gate extending over both the first and second floating gates and also extending at least partially into said gap so as to be interposed between the opposing sidewalls of the first and second floating gates;    wherein the first and second floating gates are different in size.    
     
     
         4 . The flash EEPROM cell according to  claim 3 , wherein a ratio of the size of the first floating gate to the second floating gate is {fraction (1/3)} to less than 1.  
     
     
         5 . The flash EEPROM cell according to  claim 3 , wherein said first film has a thickness of 50 through 150 Angstroms.  
     
     
         6 . The flash EEPROM cell according to  claim 3 , wherein said dielectric film is made of a combination of oxide and nitride and has the thickness of 100 through 300 Angstroms.  
     
     
         7 . The flash EEPROM cell according to  claim 3 , wherein the first and second floating gates are formed from polysilicon having a thickness of 300 through 2000 Angstroms.  
     
     
         8 . The flash EEPROM cell according to  claim 3 , wherein the first and second floating gates are formed from polysilicon having a thickness of 300 through 2000 Angstroms.  
     
     
         9 . The flash EEPROM cell according to  claim 3 , wherein the control gate is formed from polysilicon having a thickness of 300 through 2000 Angstroms  
     
     
         10 . The flash EEPROM cell according to  claim 3 , wherein: 
 the first film has a thickness of 50 through 150 Angstroms;    the dielectric film is made of a combination of oxide and nitride and has a thickness of 100 through 300 Angstroms;    the first and second floating gates are formed from polysilicon having a thickness of 300 through 2000 Angstroms; and    the control gate is formed from polysilicon having a thickness of 300 through 2000 Angstroms.    
     
     
         11 . The flash EEPROM cell according to  claim 10 , wherein the ratio of the size of the first floating gate to the second floating gate is {fraction (1/3)} to less than 1.  
     
     
         12 . The flash EEPROM cell according to  claim 3 , wherein the drain junction is formed near the first floating gate and the source junction is formed near the second floating gate.  
     
     
         13 . The flash EEPROM cell according to  claim 12 , wherein the ratio of the size of the first floating gate to the second floating gate is {fraction (1/3)} to less than 1.