Nonvolatile semiconductor memory device and data writing method therefor

Abstract

In a nonvolatile semiconductor memory device wherein a plurality of threshold voltages are set so as to store multivalued information in one memory cell, data is first written into the memory cell whose threshold voltage is the lowest as a written state from the erase level, and data is successively written into memory cells whose threshold voltages are higher.

What is claimed is:  
     
         1 . A nonvolatile semiconductor memory device comprising: 
 a program control circuit;    a plurality of data lines;    a plurality of word lines;    a plurality of nonvolatile memory cells, each of which is coupled to a corresponding data line and a corresponding word line, each of which includes a control gate and a floating gate, and each of which has a threshold voltage corresponding to data; and    a plurality of data latches, each of which is coupled to a corresponding data line and each of which stores data to be programmed in memory cells coupled to a selected word line,    wherein each of said plurality of nonvolatile memory cells has a threshold voltage in one of a plurality of threshold voltage distributions,    wherein said plurality of threshold voltage distributions includes a first threshold voltage distribution associated with an erase state, as well as a second threshold voltage distribution and a third threshold voltage distribution which are associated with respectively different program states,    wherein an absolute value of a threshold voltage within said second threshold voltage distribution is lower than an absolute value of a threshold voltage within said third threshold voltage distribution, and    wherein said program control circuit is enabled to select ones of said word lines and to bring a threshold voltage of the memory cells coupled to a selected word line into said first voltage distribution and to bring a threshold voltage of selected ones of said memory cells coupled to said selected word line, in accordance with data stored in said plurality of data latches, into said second threshold voltage distribution and to bring a threshold voltage of selected other ones of said memory cells coupled to said selected word line, in accordance with other data stored in said plurality of data latches, into said third threshold voltage distribution.    
     
     
         2 . A nonvolatile semiconductor memory device according to  claim 1 , 
 wherein an absolute value of a threshold voltage within said first threshold voltage distribution is lower than that within said second threshold voltage distribution.    
     
     
         3 . A nonvolatile semiconductor memory device comprising: 
 a control circuit;    a plurality of word lines;    a plurality of data lines; and    a plurality of nonvolatile memory cells, each of which is coupled to a corresponding data line and a corresponding word line and each of which has a threshold voltage corresponding to data,    wherein each of said plurality of nonvolatile memory cells has a threshold voltage in one of a plurality of threshold voltage distributions,    wherein said plurality of threshold voltage distributions includes a first threshold voltage distribution associated with an erase state, a second threshold voltage distribution indicative of a first data and a third threshold voltage distribution indicative of a second data in a program state,    wherein an absolute value of a threshold voltage within said second threshold voltage distribution is lower than an absolute value of a threshold voltage within said third threshold voltage distribution, and    wherein said control circuit is enabled to select ones of said word lines, and to write said first data to selected ones of said memory cells coupled to a selected word line by changing said threshold voltage thereof from a value within said first threshold voltage distribution to a value within said second threshold voltage distribution, and to write said second data to selected other ones of said memory cells coupled to said selected word line by changing said threshold voltage from a value within said first threshold voltage distribution into a value within said third threshold voltage distribution.    
     
     
         4 . A nonvolatile semiconductor memory device according to  claim 3 , 
 wherein said control circuit is enabled to check whether said threshold voltage of said ones of memory cells coupled to said selected word line have a value within said second threshold voltage distribution or not and to re-write said first data to those of said ones of memory cells which have not attained a value within said second threshold voltage distribution, after writing said first data to said ones of memory cells, and    wherein said control circuit is enabled to check whether said threshold voltage of said other ones of memory cells coupled to said selected word line have a value within said third threshold voltage distribution or not and to re-write said second data to those of said other ones of memory cells which have not attained a value within said third threshold voltage distribution, after writing said second data to said other ones of memory cells.    
     
     
         5 . A nonvolatile semiconductor memory device according to  claim 4 , 
 wherein said selected word line supplies a first voltage and those of said data lines which are coupled to said ones of memory cells not having a threshold voltage within said second threshold voltage distribution are pre-charged to a pre-charge voltage, when said control circuit is enabled to write said first data, and    wherein said selected word line supplies a second voltage and those of said data lines which are coupled to said other ones of memory cells not having a threshold voltage within said third threshold voltage distribution are pre-charged to a pre-charge voltage, when said control circuit is enabled to write said second data.    
     
     
         6 . A nonvolatile semiconductor memory device according to  claim 5 , 
 wherein said selected word line supplies a third voltage, when said control circuit is enabled to check whether said threshold voltage of said ones of memory cells coupled to said selected word line have a value within said second threshold voltage distribution or not, and    wherein said selected word line supplies a fourth voltage, when said control circuit is enabled to check whether said threshold voltage of said other ones of memory cells coupled to said selected word line have a value within said third threshold voltage distribution or not.    
     
     
         7 . A nonvolatile semiconductor memory device according to  claim 6 , 
 wherein an absolute value of a threshold voltage within said first threshold voltage distribution is lower than that within said second threshold voltage distribution.    
     
     
         8 . A nonvolatile semiconductor memory device according to  claim 3 , 
 wherein an absolute value of a threshold voltage within said first threshold voltage distribution is lower than that within said second threshold voltage distribution.