Semiconductor device having improved bias dependability and method of fabricating same

Abstract

On a semiconductor substrate is formed an insulating layer having a gate insulating region, which is coated with a first polysilicon layer having a first portion and a second portion which contacts the gate insulating region. The first portion of the first polysilicon layer is then doped with an impurity such as phosphorous. The first polysilicon layer is coated with a second insulating layer on which is formed a second polysilicon layer. A first selective etching process is provided so that a capacitive insulating layer and an upper polysilicon electrode are successively formed on the first portion of the first polysilicon layer and the second portion of the first polysilicon layer is exposed. A second selective etching process is performed so that the first and second portions of the first polysilicon layer define a lower polysilicon electrode and a gate electrode, respectively. As a result, there is produced a semiconductor device having a lower polysilicon electrode doped with an impurity of conductivity type identical to conductivity type of the polysilicon gate electrode.

What is claimed is:  
     
         1 . A semiconductor device comprising: 
 a semiconductor substrate;    an insulating layer on said substrate, said insulating layer having a gate insulating region;    a lower polysilicon electrode on said insulating layer;    a capacitive insulating layer on said lower polysilicon electrode;    an upper polysilicon electrode on said capacitive insulating layer; and    a polysilicon gate electrode on said gate insulating region, the gate electrode and said lower polysilicon electrode having equal thickness,    said lower polysilicon electrode being doped with an impurity of conductivity type identical to conductivity type of said polysilicon gate electrode.    
     
     
         2 . The semiconductor device of  claim 1 , wherein said lower polysilicon electrode has a larger area than said upper polysilicon electrode.  
     
     
         3 . The semiconductor device of  claim 1 , wherein said upper polysilicon electrode is doped with an impurity of conductivity type identical to conductivity type of said upper polysilicon electrode.  
     
     
         4 . The semiconductor device of  claim 1 , wherein said lower and upper polysilicon electrodes are doped with equal impurity dose.  
     
     
         5 . The semiconductor device of  claim 3 , wherein said impurity dose is 1×10 15 /cm 3  to 1×10 16 /cm 3 .  
     
     
         6 . The semiconductor device of  claim 1 , wherein said capacitive insulating layer has a thickness of 20 to 50 nanometers.  
     
     
         7 . The semiconductor device of  claim 1 , wherein said lower polysilicon electrode has a thickness of 100 to 250 nanometers and said upper polysilicon electrode has a thickness of 100 to 200 nanometers.  
     
     
         8 . A method of fabricating a semiconductor device, comprising the steps of: 
 a) forming a first insulating layer with a gate insulating region on a semiconductor substrate;    b) forming a first polysilicon layer on said first insulating layer and said gate insulating region, said first polysilicon layer having a first portion spaced from a second portion which contacts said gate insulating region;    c) doping an impurity into said first portion of said first polysilicon layer, said impurity having a conductivity type equal to conductivity type of said first polysilicon;    d) forming a second insulating layer on said first polysilicon layer;    e) forming a second polysilicon layer on said second insulating layer;    f) performing a first selective etching process so that a capacitive insulating layer and an upper polysilicon electrode are successively formed on said first portion of the first polysilicon layer, and said second portion of the first polysilicon layer is exposed; and    g) performing a second selective etching process so that said first and second portions of the first polysilicon layer define a lower polysilicon electrode and a gate electrode, respectively.    
     
     
         9 . The method of  claim 8 , further comprising the step of doping said second polysilicon layer with an impurity of conductivity type identical to conductivity type of the second polysilicon layer.  
     
     
         10 . The method of  claim 8 , wherein step (b) is continued until said first polysilicon layer attains a thickness of 100 to 250 nanometers, and step (e) is continued until said second polysilicon layer attains a thickness of 100 to 200 nanometers.  
     
     
         11 . The method of  claim 8 , wherein step (c) is continued until said first polysilicon layer attains an impurity dose of 1×10 15 /cm 3  to 1×10 16 /cm 3 .  
     
     
         12 . The method of  claim 9 , wherein said second polysilicon layer is doped until an impurity dose of 1×10 15 /cm 2  to 1×10 16 /cm 2  is attained.  
     
     
         13 . The method of  claim 8 , wherein step (d) is continued until said second insulating layer attains a thickness of 20 to 50 nanometers.