Method of forming a memory cell with self-aligned contacts

Abstract

In one embodiment, the present invention provides a method of forming a dynamic random access memory device which utilizes self-aligned contact pads 40 a and 40 b for the bit line and storage node contacts. A transfer gate 14 is formed at the fact of a semiconductor region 30. The semiconductor 30 includes a bit line contact region 44 and storage node contact region adjacent opposite edges of the transfer gate 14. Transfer gate 14 is surrounded with an insulating material 34/38. A conductive layer 40 is formed over the transfer gate 14, over the bit line contact region 44 and over the storage node contact region. This conductive layer 40 is then etched so that a first portion 40 a of the conductive layer 40 provides an electrical contact to the bit line contact region 44 and a second portion 40 b of the conductive layer 40 provides an electrical contact to the storage node contact region. The bit line 18 and storage node electrode 22 can then be formed in electrical contact with the first and second portions of the conductive layer 40 a and 40 b , respectively.

What is claimed is:  
     
         1 . A method of forming a memory cell, the method comprising the steps of: 
 Forming a transfer gate at the face of a semiconductor region, the semiconductor region including a bit line contact region and storage node contact region wherein the transfer gate includes a first edge adjacent the bit line contact region and a second edge adjacent the storage node contact region;    surrounding the transfer gate with an insulating material;    forming a conductive layer over the transfer gate, over the bit line contact region and over the storage node contact region;    forming a masking layer over the conductive layer;    etching the masking layer to form a bit line contact window over a portion of the conductive layer;    etching the conductive layer such that a portion of the conductive layer provides an electrical contact to the bit line contact region and a second portion of the conductive layer provides an electrical contact to the storage node contact region;    forming a bit line electrically coupled to the first portion of the conductive layer; and    forming a storage node electrode electrically coupled to the second portion of the conductive layer.    
     
     
         2 . The method of  claim 1  wherein the step of forming a transfer gate comprises depositing a conductive layer, depositing an insulating layer and patterning and etching the conductive layer and the insulating layer.  
     
     
         3 . The method of  claim 2  wherein the conductive layer comprises a multilayer conductor.  
     
     
         4 . The method of  claim 3  wherein the step of depositing a conductive layer comprises the steps of depositing a polysilicon layer and then forming a silicide layer over the polysilicon layer.  
     
     
         5 . The method of  claim 2  wherein the insulating layer comprises a nitride layer.  
     
     
         6 . The method of  claim 2  wherein the step of surrounding the transfer gate comprises said step of depositing an insulating layer and further comprises the step of forming a sidewall insulator adjacent sidewalls of the transfer gate.  
     
     
         7 . The method of  claim 6  wherein the sidewall insulator comprises an oxide, sidewall insulator.  
     
     
         8 . The method of  claim 1  wherein the step of forming a conductive layer comprises the step of depositing a polysilicon layer.  
     
     
         9 . The method of  claim 1  wherein the conductive layer physically abuts the bit line contact region and the storage node contact region.  
     
     
         10 . A method of forming a memory device, the method comprising the steps of: 
 forming first and second transfer gates at the face of a semiconductor region, the semiconductor region including a bit line contact region located between the first and second transfer gates, a storage node contact region located adjacent the first transfer gate, and a second storage node contact region located adjacent the second transfer gate;    surrounding the transfer gate with an insulating material;    forming a conductive layer over the transfer gate, over the bit line contact region and over the storage node contact region;    forming a masking layer over the conductive layer;    removing a portion of the masking layer so as to expose a portion of the conductive layer over the bit line contact regions and over portions of the first and second transfer gates which are adjacent to the bit line contact region;    forming a bit line layer over the masking layer and the exposed portion of the conductive layer;    forming a bit line by patterning and etching the bit line layer, the patterning and etching step exposing a portion of the conductive layer between the masking layer and the bit line; and    removing the exposed portion of the conductive layer using the masking layer as a mask.    
     
     
         11 . The method of  claim 10  and further comprising the steps of: 
 Removing a portion of the masking layer over the first storage node contact region; and  
 forming a storage node electrode of a storage capacitor in electrical contact with the first storage node contact region.  
 
     
     
         12 . The method of  claim 10  and further comprising the step of forming a sidewall insulator along sidewalls of the bit line.  
     
     
         13 . A method of forming a memory device, the method comprising the steps of; 
 forming a conductive gate layer over a semiconductor region, the conductive layer being electrically insulated from the semiconductor region;    forming oxide sidewalls along sidewalls of the gate;    forming a polysilicon layer over the gate and abutting a bit line contact portion of the semiconductor region adjacent a first edge of the gate, the polysilicon layer also abutting a storage node contact portion of the semiconductor region adjacent an opposite edge of the gate;    forming an oxide layer over the polysilicon layer;    forming a bit line contact window by removing a portion of the oxide layer to expose a bit line contact portion of the polysilicon layer over the bit line contact portion of the semiconductor region;    forming a bit line conductor in electrical contact with the exposes portion of the polysilicon layer, the step of forming a bit line conductor including an etching step which electrically isolates bit line contact portion of the polysilicon layer from the remainder of the polysilicon layer;    forming a storage node conductor in electrical contact with a portion of the polysilicon layer over the storage node contact region of the semiconductor region;    forming a dielectric over the storage node conductor; and    forming a cell plate conductor over the dielectric.    
     
     
         14 . The method of  claim 12  and further comprising the step of forming an oxide sidewall along sidewalls of the bit line conductor.  
     
     
         15 . The method of  claim 13  wherein the storage node conductor is formed so as to about the oxide sidewall along the bit line conductor.  
     
     
         16 . A memory device comprising; 
 an active region disposed in a semiconductor region, the active region surrounded by a field oxide region,    a transfer gate over an upper surface of the active region, the transfer gate including a top surface and sidewall, the transfer gate spaced from the field oxide region by a contact region within the active region,    a top surface insulator disposed along the top surface of the transfer gate, the top surface insulator comprising a first material;    a sidewall insulator disposed along the sidewall of the transfer gate, the sidewall insulator comprising a second material which is different than the first material;    a conductive pad extending from over a portion of the field oxide region to over a portion of the insulator disposed along the top surface of the transfer gate, the conductive pad abutting the contact region of the active area; and    a storage node conductor abutting the conductive pad, the storage node conductor comprising one plate of a capacitor.    
     
     
         17 . The device of  claim 15  wherein the storage node conductor is formed in the shape of a crown cell conductor.  
     
     
         18 . The device of  claim 15  wherein the conductive pad comprises a polysilicon pad.  
     
     
         19 . The device of  claim 15  wherein the conductive pad abuts the sidewall insulator.  
     
     
         20 . The device of  claim 15  wherein the storage node conductor overlies a portion of the field oxide, the storage node conductor extending along the field oxide beyond the conductive pad.  
     
     
         21 . The device of  claim 15  and further comprising a bit line conductor electrically coupled to a portion of the active area, the storage node conductor overlying a portion of the bit line conductor and electrically insulated therefrom.  
     
     
         22 . The device of  claim 20  and further comprising a bit line sidewall region formed along sidewalls of the bit line conductor.  
     
     
         23 . The device of  claim 16  wherein the top surface insulator comprises a nitride material and the sidewall insulator comprises an oxide material.  
     
     
         24 . A memory device comprising; 
 a first transfer gate disposed over an upper surface of a semiconductor region active region, the first transfer gate including a top surface and sidewall,    a first top surface insulator disposed along the top surface of the first transfer gate, the first top surface insulator comprising a first material;    a first sidewall insulator disposed along the sidewall of the first transfer gate, the first sidewall insulator comprising a second material which is different than the first material;    a second transfer gate disposed over the upper surface of the semiconductor region, the second transfer gate including a top surface and a sidewall, the second transfer gate spaced from the first transfer gate by a contact region within the active region;    a second top surface insulator disposed along the top surface of the second transfer gate, the second top surface insulator comprising the first material;    a second sidewall insulator disposed along the sidewall of the second transfer gate, the second sidewall insulator comprising the second material;    a conductive pad extending over a portion of the first top surface insulator, the first sidewall insulator, the contact region within the active area, the second sidewall insulator, and a portion of the second top surface insulator, the conductive pad abutting the contact region of the active area; and    a bit line conductor electrically coupled to the conductive pad, the bit line conductor comprising a bit line within a memory array.    
     
     
         25 . The device of  claim 24  wherein the conductive pad comprises a polysilicon pad.  
     
     
         26 . The device of  claim 24  wherein the conductive pad abuts the sidewall insulator.  
     
     
         27 . The device of  claim 24  wherein the conductive pad is aligned with the bit line conductor.  
     
     
         28 . The device of  claim 24  and further comprising a bit line sidewall region formed along sidewalls of the bit line conductor.  
     
     
         29 . The device of  claim 24  wherein the first material comprises a nitride material and the second material comprises an oxide material.