High side and low side guard rings for lowest parasitic performance in an H-bridge configuration

Abstract

A method of minimizing parasitics in an MOS device caused by the formation of a bipolar transistor within the MOS devices and the device, primarily for a polyphase bridge circuit. For the low side device, a substrate of a first conductivity type is provided having a first buried layer of opposite conductivity type thereon. A second buried layer of the first conductivity type is formed over the first buried layer and a further layer of the first conductivity type is formed over the second buried layer. A sinker extending through the further layer to the first buried layer is formed to isolate the second buried layer and the further layer from the substrate. Formation of an MOS device in the further layer including source, drain and gate regions is completed and the sinker is connected to a source terminal of the device. The second buried layer is formed either by coimplanting a p-type dopant and an n-type dopant with one of the dopant having a higher diffusion rate than the other or by implanting and diffusing one of the two dopants first to form one layer and then implanting and diffusing the other dopant to form the second layer. The preferred dopants are boron as the p-type dopant and antimony as the n-type dopant.

1 . A method of minimizing parasitics in an MOS device caused by the formation of a bipolar transistor within the MOS device which comprises the steps of: 
 (a) providing a substrate of a first conductivity type having a first buried layer of opposite conductivity type thereon;    (b) forming a second buried layer of said first conductivity type over said first buried layer;    (c) forming a further layer of said first conductivity type over said second buried layer;    (d) forming source and drain regions in said further layer;    (e) forming a sinker extending through said further layer to said first buried layer to isolate said second buried layer and said further layer from said substrate; and    (f) completing formation of an MOS device in said further layer including source and drain regions.    
     
     
         2 . The method of  claim 1  wherein said sinker is a portion of a high side MOS device and said sinker is connected to said source region.  
     
     
         3 . The method of  claim 1  wherein said sinker is a portion of a low side MOS device and said sinker is connected to said source region.  
     
     
         4 . The method of  claim 2  wherein said MOS device is the low side of a polyphase bridge circuit.  
     
     
         5 . The method of  claim 3  wherein said MOS device is the high side of a polyphase bridge circuit.  
     
     
         6  The method of  claim 4  further including a power supply having first and second terminals, said first terminal being positive relative to said second terminal, said source region being coupled to said second terminal.  
     
     
         7 . The method of  claim 6  further including a load, said drain region being coupled to said load.  
     
     
         8 . The method of claim,  5  further including a power supply having first and second terminals, said first terminal being positive relative to said second terminal, said drain region being coupled to said first terminal.  
     
     
         9 . The method of  claim 8  further including a load, said source region being coupled to said load.  
     
     
         10 . The method of  claim 1  wherein said first and second buried layers are formed by coimplanting a p-type dopant and an n-type do pant with one of said dopants having a higher diffusion rate than the other.  
     
     
         11 . The method of  claim 10  wherein said p-type dopant has a higher diffusion rate than the n-type dopant.  
     
     
         12 . The method of  claim 11  wherein said p-type dopant is boron and said n-type dopant is antimony.  
     
     
         13 . The method of  claim 1  wherein said first and second buried layers are formed by implanting a dopant of a first conductivity type followed by implanting a dopant thereover of a second conductivity type.  
     
     
         14 . The method of  claim 13  wherein said dopant of a first conductivity type is n-type and said dopant of said second conductivity type is p-type.  
     
     
         15 . The method of  claim 14  wherein said p-type dopant is boron and said n-type dopant is antimony.  
     
     
         16  An MOS device which comprises. 
 (a) a substrate of a first conductivity type having a first buried layer of opposite conductivity type thereon;  
 (b) a second buried layer of said first conductivity type over said first buried layer;  
 (c) a further distinct layer of said first conductivity type over said second buried layer;  
 (d) a sinker extending through said further distinct layer to said first buried layer to isolate said second buried layer and said further layer from said substrate; and  
 (e) source, drain and gate regions in said further layer.  
 
     
     
         17 . The device of  claim 16  wherein said sinker is coupled to said source region.  
     
     
         18 . The device of  claim 17  wherein said MOS device is the low side of a polyphase bridge circuit, further including a power supply having first and second terminals, said first terminal being positive relative to said second terminal, said source region being coupled to said second terminal and a load, said drain region being coupled to said load and said source region being coupled to said second terminal.  
     
     
         19 . The device of  claim 17  wherein said MOS device is the high side of a polyphase bridge circuit, further including a power supply having first and second terminals, said first terminal being positive relative to said second terminal, said drain region being coupled to said first terminal and said source region being coupled to said load.  
     
     
         20 . An MOS device which comprises: 
 (a) a substrate of a first conductivity type having a first spaced apart buried layer portions of opposite conductivity type thereon;    (b) a second buried layer of said first conductivity type over said first buried layer having a pair of spaced apart portions;    (c) a further distinct layer of said first conductivity type over said second buried layer having a pair of spaced apart portions;    (d) a pair of sinkers, each sinker extending through a different portion of said further distinct layer to a different portion of said first buried layer to isolate said second buried layer and said further layer from said substrate and from the other of said first, second and further distinct layer portions; and    (e) source, drain and gate regions in each of said further layer portions.    
     
     
         21 . The device of  claim 16  wherein each of said sinkers is coupled to a different one of said source regions.  
     
     
         22 . The device of  claim 21  wherein said MOS device is the high and low side of a polyphase bridge circuit, further including a power supply having first and second terminals, said first terminal being positive relative to said second terminal, said source region of said low side device being coupled to said second terminal and a load, said drain region of said low side device being coupled to said load and said source region being coupled to said second terminal and said drain region of said high side device being coupled to said first terminal and said source region being coupled to said load.  
     
     
         23 . An MOS device which comprises: 
 (a) a substrate of a first conductivity type having a first buried layer of opposite conductivity type thereon,    (b) a further distinct layer of said first conductivity type over said second buried layer;    (c) a sinker extending through said further distinct layer to said first buried layer to isolate said further layer from said substrate; and    (d) source, drain and gate regions in said further layer.    
     
     
         24 . The device of  claim 23  wherein said sinker is coupled to said source region.  
     
     
         25 . The device of  claim 24  wherein said MOS device is the low side of a polyphase bridge circuit, further including a power supply having first and second terminals, said first terminal being positive relative to said second terminal, said source region being coupled to said second terminal and a load, said drain region being coupled to said load and said source region being coupled to said second terminal.  
     
     
         26 . The device of  claim 24  wherein said MOS device is the high side of a polyphase bridge circuit, further including a power supply having first and second terminals, said first terminal being positive relative to said second terminal, said drain region being coupled to said first terminal and said source region being coupled to said load.