Method for manufacturing a chip scale package

Abstract

A method for manufacturing a chip scale package comprises preparing a tape wiring board that includes a polyimide tape having top and bottom surfaces, Cu traces formed on the bottom surface of the tape, a window formed in the tape to enable the Cu traces to be connected to a semiconductor chip attached below the board, multiple connection holes formed in the tape to expose portions of the Cu traces therethrough and define solder ball mounting pads, and an elastomer chip carrier attached to the bottom surface of the tape. The method includes applying either a pre-flux or a cover sheet over the solder ball mounting pads. The pre-flux and the cover sheet each prevents the solder ball mounting pads being plated with gold. This, in turn, prevents the formation of intermetallic compounds in the solder balls so that the bond strength between the solder balls and a pad to which they attach is improved.

What is claimed is:  
     
         1 . A method for manufacturing a chip scale package, the method comprising: 
 (A) preparing a tape wiring board comprising a strip of polyimide tape having a plurality of copper traces on a bottom surface of the tape, a window through the tape having portions of the copper traces extending across the window, a plurality of connection holes through the tape exposing other portions of the copper traces through the holes, and an elastomer chip carrier on a bottom surface of the tape;    (B) applying a pre flux to the portions of the copper traces exposed through the connection holes;    (C) plating the copper traces extending across the window with gold (Au) to define beam leads;    (D) attaching a semiconductor chip to the elastomer chip carrier;    (E) bonding the gold plated beam leads to the semiconductor chip through the window;    (F) encapsulating the bonding area between the beam leads and the semiconductor chip; and,    (G) forming a solder bump on each of the portions of the copper traces exposed through the connection holes.    
     
     
         2 . The method of  claim 1 , wherein attaching the semiconductor chip to the elastomer chip carrier comprises melting a bottom surface of the carrier and contacting a surface of the chip to the melted elastomer.  
     
     
         3 . The method of  claim 2 , wherein attaching the semiconductor chip to the elastomer chip carrier comprises attaching an active surface of the chip having connection pads on a periphery thereof to the chip carrier such that the periphery overhangs the chip carrier and is exposed below the window in the tape.  
     
     
         4 . The method of  claim 1 , wherein encapsulating the bonding area between the beam leads and the semiconductor chip comprises dispensing a viscous liquid encapsulant onto the area of the bonded parts.  
     
     
         5 . The method of  claim 1 , wherein forming the solder bumps further comprises: 
 (G1) placing solder balls on the respective portions of the Cu traces that are exposed through the connection holes, each such portion having the pre flux solution thereon;    (G2) reflow soldering the solder balls so that each solder ball is bonded to a respective copper trace portion exposed through a connection hole and forms a solder bump thereon; and,    (G3) washing off any remaining pre flux and other impurity residues around the solder bumps.    
     
     
         6 . The method of  claim 5 , wherein the reflow soldering process comprises an infrared reflow method.  
     
     
         7 . A method for manufacturing a chip scale package, the method comprising: 
 (A) preparing a tape wiring board comprising a polyimide tape having copper traces on a bottom surface of the tape, a window through the tape having portions of the copper traces extending across window, a plurality of connection holes in the tape exposing other portions of the copper traces, and an elastomer chip carrier on the bottom surface of the tape;    (B) attaching a cover film to the top surface of the polyimide tape;    (C) plating the portions of the copper traces extending across the window with gold (Au) to define beam leads;    (D) removing the cover film from the polyimide tape;    (E) attaching the semiconductor chip to the elastomer;    (F) bonding the beam leads to the semiconductor chip;    (G) encapsulating the bonding area between the beam leads and the semiconductor chip; and,    (H) forming a solder bump on each of the solder ball mounting pads.    
     
     
         8 . The method of  claim 7 , wherein the cover film is attached to the top surface of the polyimide tape such that it does not cover the window.  
     
     
         9 . The method of  claim 7 , wherein the cover film comprises an adhesive layer.  
     
     
         10 . The method of  claim 9 , wherein the layer of adhesive on the cover film is an ultraviolet-light-sensitive adhesive that releases its adhesion upon exposure to ultraviolet light, and wherein removing the cover film from the polyimide tape comprises irradiating the cover film with an ultraviolet light.  
     
     
         11 . The method of  claim 7 , wherein the semiconductor chip is directly attached to the elastomer chip carrier by heating a bottom surface of the elastomer chip carrier until the elastomer reaches a molten state, contacting a surface of the chip to the molten elastomer, and cooling the molten elastomer until it solidifies.  
     
     
         12 . The method of  claim 11 , wherein attaching the semiconductor chip to the elastomer chip carrier comprises attaching an active surface of the chip having electrical connection pads around periphery thereof to the bottom surface of the chip carrier such that the periphery of the chip overhangs the chip carrier and is exposed below the window in the tape.  
     
     
         13 . The method of  claim 7 , wherein encapsulating the bonding area between the beam leads and the semiconductor chip comprises dispensing a viscous liquid encapsulant onto the area of the bonded parts.  
     
     
         14 . The method of  claim 7 , wherein forming a solder bump on the solder ball mounting pads comprises: 
 (H1) applying a flux to the solder ball mounting pads;    (H2) placing solder balls on the flux;    (H3) reflow soldering the solder balls so that the solder balls bond to the respective solder ball mounting pads and form solder bumps thereon; and,    (H4) washing off any remaining flux and other impurity residues around the solder bumps.    
     
     
         15 . The method of  claim 14 , wherein the reflow soldering comprises an infrared reflow method.  
     
     
         16 . A chip scale package, comprising: 
 a tape wiring board comprising a strip of polyimide tape having top and bottom surfaces;    copper traces formed on the bottom surface of the tape, the copper traces having gold plated portions and non-gold plated portions;    the polyimide tape having a window formed through it such that the gold plated portions of the copper traces extend across the window for connection to a semiconductor chip through the window;    the polyimide tape having a plurality of connection holes formed through it, each connection hole exposing a non-gold plated portion of the copper trace there-through, each exposed non-gold plated portion defining a solder ball mounting pad;    a semiconductor chip bonded to the bottom surface of the polyimide tape;    an encapsulant for encapsulating the bonding area between the polyimide tape and the semiconductor chip; and,    a solder bump formed on each solder ball mounting pad.    
     
     
         17 . The chip scale package of  claim 16 , further comprises an elastomer chip carrier interposed between the bottom surface of the polyimide tape inside a periphery of the window and an upper surface of the semiconductor chip.  
     
     
         18 . The chip scale package of  claim 16 , wherein the gold plated and the non-gold plated portions of the copper traces are formed by applying a pre flux on the solder ball mounting pads and then plating the copper traces with gold (Au).  
     
     
         19 . The chip scale package of  claim 16 , wherein the gold plated and the non-gold plated portions of the copper traces are formed by attaching a cover film to the top surface of the polyimide tape and then plating the copper traces with gold (Au).