Multi-level circuit structure

Abstract

In a semiconductor device, a conductive structure comprising an interconnect and an overlying plug integrally extending therefrom is provided. The structure can be provided by a damascene process, wherein an opening is defined in insulation deep enough to accommodate the height of an interconnect and its overlying plug. The opening is filled with metal, and non-plug areas of the metal are then recessed down to a standard interconnect height within the trench. The full height of the metal is retained at the plug site. Oxide is then deposited over the recessed portions. Alternatively, a continuous metal layer is provided that is deep enough to accommodate the height of an interconnect and its overlying plug. The metal is then etched to form the interconnect/plug structure, and insulation is deposited thereover. Multiple structures may be provided at the same level using these processes, and multiple levels of these structures may be similarly provided.

What is claimed is:  
     
         1 . A method of forming at least one conductive plug in a semiconductor device, comprising: 
 including an insulator material as part of said semiconductor device;    defining a trench in said insulator material, said trench having a length sufficient to accommodate an interconnect, and said trench further having a depth sufficient to accommodate said interconnect and said at least one plug over said interconnect anywhere along said length;    filling said trench with a conductive material;    recessing said conductive material except in at least one site respectively designated for said at least one plug; and    providing insulation within said trench and over a recessed portion of said conductive material.    
     
     
         2 . A method of processing a circuit device including insulation material, comprising: 
 etching a plug site in said insulation material of said circuit device;    etching an interconnect site in said insulation material under said plug site;    initiating a deposition of a metal into said interconnect site; and    continuing said deposition of said metal into said plug site.    
     
     
         3 . The method in  claim 2 , further comprising contacting said metal in said plug site with an interconnect over said plug site.  
     
     
         4 . The method in  claim 2 , further comprising: 
 etching said metal from said plug site;    filling said plug site with an oxide; and    contacting said oxide in said plug site with an interconnect over said plug site.    
     
     
         5 . A method of constructing a semiconductor device, comprising: 
 providing a first plurality of integrated interconnect/plug structures within a first insulation layer of said semiconductor device; and    replacing a plug portion of at least one interconnect/plug structure of said first plurality with additional insulation.    
     
     
         6 . The method in  claim 5 , wherein said step of providing a first plurality of integrated interconnect/plug structures comprises providing said first plurality of integrated interconnect/plug structures using a damascene process.  
     
     
         7 . The method in  claim 6 , further comprising providing a plurality of interconnects on said-first insulation layer.  
     
     
         8 . The method in  claim 7 , wherein said step of providing a plurality of interconnects comprises providing a second plurality of integrated interconnect/plug structures.  
     
     
         9 . The method in  claim 8 , wherein said step of providing a second plurality of integrated interconnect/plug structures further comprises: 
 providing a conductive layer on said first insulation layer, wherein said conductive layer has a height defining an interconnect height and a plug height; and    etching said second plurality of integrated interconnect/plug structures from said conductive layer.    
     
     
         10 . The method in  claim 9 , wherein said step of providing a second plurality of integrated interconnect/plug structures comprises providing said second plurality of integrated interconnect/plug structures within a second insulation layer.  
     
     
         11 . The method in  claim 10 , wherein said step of providing said second plurality of integrated interconnect/plug structures within a second insulation layer comprises flowing insulation between each of said second plurality of integrated interconnect/plug structures.  
     
     
         12 . The method in  claim 10 , wherein said step of providing said second plurality of integrated interconnect/plug structures within a second insulation layer comprises spinning glass between each of said second plurality of integrated interconnect/plug structures.  
     
     
         13 . A method of integrating an interconnect and an overlying plug in a semiconductor wafer structure, comprising: 
 etching an elongated trench from at least one layer of said semiconductor wafer structure;    filling said trench with metal;    masking a portion of said trench; and    etching some of said metal from an unmasked portion of said trench.    
     
     
         14 . The method in  claim 13 , further comprising a step of depositing insulation within said trench.  
     
     
         15 . A method of forming a conductive plug over an interconnect in a semiconductor device, comprising: 
 providing a layer of insulation as a part of said semiconductor device, said layer of insulation having a thickness sufficient to accommodate a plug site and an interconnect site;    etching said plug site from said layer of insulation; and    filling said plug site with conductive material.    
     
     
         16 . The method in  claim 15 , wherein said step of etching said plug site from said layer of insulation comprises further etching said interconnect site from said layer of insulation.  
     
     
         17 . The method in  claim 16 , wherein said step of filling said plug site with conductive material comprises filling said interconnect site with said conductive material.  
     
     
         18 . A method of forming a conductive plug over an interconnect in a memory device, comprising: 
 providing a layer of insulation as a part of said memory device;    etching a via from said layer of insulation;    etching a portion of said layer of insulation from an area lateral to and extending from said via;    filling said via and said area with conductive material; and    etching said conductive material from said area.    
     
     
         19 . The method in  claim 18 , further comprising: 
 masking said via before said step of etching said conductive material; and    filling said area with additional insulation.    
     
     
         20 . A method of forming a conductive plug over an interconnect in an electronic device, comprising: 
 providing a layer of insulation over a portion of said electronic device;    etching a plug site from said layer of insulation;    continuing to etch an interconnect site; and    filling said plug site with metal.    
     
     
         21 . The method in  claim 20 , wherein said step of filling said plug site comprises initially filling said interconnect site with said metal.  
     
     
         22 . A method of processing a wafer having an insulation layer flanking conductive paths and configured to receive a patterned first mask on top of said insulation layer, wherein said first mask is configured to expose plug sites within said insulation layer, said method comprising: 
 allowing said conductive paths to extend to said top of said insulation layer of said wafer; and    patterning a second mask on said insulation layer, wherein said second mask is generally inverse to said first mask.    
     
     
         23 . The method in  claim 22 , wherein said step of patterning a second mask comprises masking said plug sites.  
     
     
         24 . The method in  claim 23 , wherein said step of patterning a second mask comprises exposing portions of said conductive paths external to said plug sites.  
     
     
         25 . The method in  claim 24 , wherein said step of patterning a second mask comprises exposing said portions of said conductive paths and portions of said insulation layer external to said plug sites.  
     
     
         26 . The method of  claim 25 , further comprising a step of etching said portions of said conductive paths.  
     
     
         27 . The method of  claim 26 , wherein said etching step further comprises selectively etching said portions of said conductive paths to a general exclusion of said insulation layer.  
     
     
         28 . A method of allowing electrical connection to a conductive path of a semiconductor apparatus, comprising 
 providing a dielectric as a part of processing said semiconductor apparatus;    etching an opening in said dielectric to a depth configured to accommodate said conductive path and a plug over said path;    filling said opening with conductive material;    designating a conductive path site comprising a lower portion of said conductive material within said opening;    designating a plug site comprising a first upper portion of said conductive material within said opening;    etching a second upper portion of said conductive material next to said first upper portion; and    avoiding etching said plug site while etching said second upper portion.    
     
     
         29 . The method in  claim 28 , wherein said step of avoiding etching said plug site comprises masking said plug site.  
     
     
         30 . The method in  claim 29 , further comprising a step of avoiding etching said lower portion of said conductive material while etching said second upper portion.  
     
     
         31 . A system of interconnects for a semiconductor structure, comprising: 
 a first interconnect within said semiconductor structure; and    a second interconnect coupled to said first interconnect through a plug, wherein 
 said second interconnect and said plug define an integral structure.  
   
     
     
         32 . The system in  claim 31 , wherein at least a portion of said second interconnect is under said first interconnect.  
     
     
         33 . The system in  claim 32 , wherein said portion of said second interconnect is coupled to said first interconnect through said plug.  
     
     
         34 . The system in  claim 33 , farther comprising a third interconnect laterally contacting a first insulator and at least partially isolated from said first interconnect by a second insulator.  
     
     
         35 . The system in  claim 34 , wherein said second interconnect laterally contacts said first insulator.  
     
     
         36 . The system in  claim 35 , wherein said second insulator laterally contacts said plug, and wherein said second insulator is over a part of said second interconnect.  
     
     
         37 . A portion of a memory array, comprising at least one integrated structure comprising a first interconnect within said memory array and an electrical connector extending upward.  
     
     
         38 . A portion of a semiconductor device comprising: 
 at least two portions of insulation defining: 
 a first opening within said semiconductor device, defining: 
 a first plug site, and  
 a first interconnect site in communication with said first plug site,  
 wherein said first plug site and said first interconnect site are filled with a continuous amount of conductive material; and  
 
 a second opening lateral to said first opening, said second opening defining: 
 a second plug site filled with at least one portion of said at least two portions of insulation, and  
 a second interconnect site in communication with said second plug site, wherein said second interconnect site is filled with said conductive material.  
 
   
     
     
         39 . A level of interconnects for a semiconductor device, comprising: 
 a layer of insulation defining a plurality of trenches within said semiconductor device, wherein each trench of said plurality defines a lower portion and an upper portion, and wherein: 
 said lower portion is filled with metal,  
 said metal extends up into at least one area of said upper portion, and  
 said upper portion is filled with oxide except in said at least one area.  
   
     
     
         40 . The level of interconnects in  claim 39 , wherein said each trench is lined with a barrier layer.  
     
     
         41 . The level of interconnects in  claim 39 , wherein said each trench is lined with an adhesion layer.  
     
     
         42 . A multi-layer interconnect structure for a memory apparatus, comprising: 
 a first layer of insulation forming a part of said memory apparatus;    a second layer of insulation over said first layer;    a first conductive path within said first layer of insulation, wherein said first conductive path comprises a first integral plug extending toward said second layer;    a discrete portion of insulation within said first layer, over said first conductive path, and under said second layer of insulation; and    a second conductive path within said second layer of insulation, wherein said second conductive path contacts said first plug.    
     
     
         43 . The multi-layer interconnect structure of  claim 42 , wherein said second layer of insulation has a top, and wherein said second conductive path comprises a second integral plug extending toward said top.  
     
     
         44 . A semiconductor device, comprising: 
 a first surface of said semiconductor device;    a first conductive element on said first surface;    a second surface below said first surface; and    a second conductive element on said second surface, wherein said second conductive element comprises a first part extending to said first conductive element and a second part integral to said first part and recessed from said first surface.    
     
     
         45 . The semiconductor device in  claim 44 , further comprising: 
 a first insulator lateral to said second conductive element; and    a second insulator above said second part of said second conductive element;    wherein a top of said first insulator and a top of said second insulator define said second surface.    
     
     
         46 . The semiconductor device in  claim 45 , wherein said first conductive element is a conductive line.  
     
     
         47 . The semiconductor device in  claim 45 , wherein said second conductive element is an interconnect.  
     
     
         48 . A portion of circuitry, comprising: 
 a surface;    an insulation layer over said surface;    a conductive element over said insulation layer; and    a conductive circuitry structure comprising: 
 a first part extending from said surface, through said insulation layer, to said conductive element, and  
 a second part integral to said first part, insulated from said conductive element, and extending laterally from said first part.  
   
     
     
         49 . The portion of circuitry in  claim 48 , wherein said surface is a semiconductor substrate.  
     
     
         50 . A method of forming a vertical and horizontal electrical connection structure for a semiconductor device, comprising: 
 forming an insulating layer onto a part of said semiconductor device;    defining a trench in said insulating layer;    filling said trench with a conductor; and    reducing a height of said conductor within said trench at all but at least one location.    
     
     
         51 . A method of forming a lateral interconnect circuitry structure including at least one vertically-protruding plug, comprising: 
 forming a circuitry insulating layer having a laterally-extending recess therein;    filling said laterally-extending recess with a conductive material; and    removing a depth of said conductive material from said recess except at at least one location.    
     
     
         52 . The method in  claim 51 , further comprising a step of retaining at least some of said conductive material in a portion of said recess that is external to said at least one location.  
     
     
         53 . A method of treating an in-process circuit, comprising: 
 forming a trench from an insulation material;    sputtering an interconnect material into said trench, wherein said sputtering step occurs at a temperature ranging from 510° C. to 520° C.;    forming a plug over said interconnect material; and    refraining from planarizing said in-process circuit between said sputtering step and said step of forming a plug.    
     
     
         54 . The method in  claim 53 , wherein said sputtering step comprises sputtering aluminum.  
     
     
         55 . The method in  claim 54 , wherein said step of forming a trench comprises forming a trench having a depth sufficient to accommodate a height of an interconnect and a height of a plug anywhere along said trench; and wherein said step of forming a plug comprises: 
 continuing to sputter aluminum into said trench; and    recessing a surface of said aluminum except at at least one region representing at least one respective plug site.    
     
     
         56 . A multi-level circuit structure, comprising: 
 a first part of said circuit structure positioned in a lower level of a semiconductor device and isolated from a higher level of said device; and    a second part of said circuit structure seamlessly coupled to said first part, wherein said second part extends to said higher level.    
     
     
         57 . The structure in  claim 56 , wherein said first part and said second part are metal.  
     
     
         58 . A multi-axial circuit structure, comprising: 
 a first part of said circuit structure extending primarily along a first axis;    a second part of said circuit structure integral to said first part, wherein said second part extends upward from said first part primarily along a second axis perpendicular to said first axis.