Method of fabricating isolation trenches in a semiconductor substrate

Abstract

A method of fabricating isolation trenches in a semiconductor. The width of an isolation trench (FIGS. 6 and 7 ) is defined by the width between a field oxide layer ( 104 ) and a pad oxide layer ( 101 a ), whereby the size of the isolation trench is effectively reduced.

What is claimed is:  
     
         1 . A method of fabricating isolation trenches in a semiconductor substrate, the method comprising: 
 forming a first isolation layer on said semiconductor substrate;    forming a mask layer on said first isolation layer;    removing portions of said first isolation layer adjacent and underlying edge portions of said mask layer, thereby undermining edge portions of said mask layer and leaving a portion of said first isolation layer underlying said mask layer;    forming a second isolation layer over said semiconductor substrate and said mask layer, and beneath undermined portions of said mask layer and adjacent to the remaining portions of said first isolation layer;    removing portions of said second isolation layer to form spacers adjacent to said mask layer;    forming isolation regions adjacent to said spacers, in said semiconductor substrate;    removing said spacers and said mask layer to expose the remaining portions of said first isolation layer and said semiconductor substrate; and    removing portions of said semiconductor substrate to form isolation trenches between the remaining portions of said first isolation layer and said isolation regions, said isolation trenches extending into said semiconductor substrate.    
     
     
         2 . The method as claimed in  claim 1 , wherein forming said mask layer comprises the steps of: 
 forming a third isolation layer on said first isolation layer; and    patterning and etching said third isolation layer thereby forming said mask layer.    
     
     
         3 . The method as claimed in  claim 2 , wherein said first isolation layer is a pad oxide layer; said second and third isolation layers are nitride layers; and said isolation regions are field oxide layers.  
     
     
         4 . The method as claimed in  claim 3 , wherein said spacers and said mask layer are removed by wet etching.  
     
     
         5 . The method as claimed in  claim 3 , wherein said field oxide layers are formed by selectively oxidizing said semiconductor substrate.  
     
     
         6 . The method as claimed in  claim 1 , further filling said isolation trenches with fourth isolation layers.  
     
     
         7 . The method as claimed in  claim 6 , wherein said fourth isolation layers are oxide layers.  
     
     
         8 . A method of fabricating isolation trenches in a semiconductor substrate, the method comprising: 
 forming a first isolation layer on said semiconductor substrate;    forming a mask layer on said first isolation layer;    removing portions of said first isolation layer adjacent and underlying edge portions of said mask layer, thereby undermining edge portions of said mask layer and leaving a portion of said first isolation layer underlying said mask layer;    forming a second isolation layer over said semiconductor substrate and said mask layer, and beneath undermined portions of said mask layer and adjacent to the remaining portions of said first isolation layer;    removing portions of said second isolation layer to form spacers adjacent to said mask layer;    forming isolation regions adjacent to said spacers, in said semiconductor substrate;    removing said spacers, said mask layer, and portions of said semiconductor substrate between the remaining portions of said first isolation layer and said isolation regions thereby forming isolation trenches deep into said semiconductor substrate.    
     
     
         9 . The method as claimed in  claim 8 , wherein forming said mask layer comprises the steps of: 
 forming a third isolation layer on said first isolation layer; and    patterning and etching said third isolation layer thereby forming said mask layer.    
     
     
         10 . The method as claimed in  claim 9 , wherein said first isolation layer is a pad oxide layer; said second and third isolation layers are nitride layers; and said isolation regions are field oxide layers.  
     
     
         11 . The method as claimed in  claim 10 , wherein said field oxide layers are formed by selectively oxidizing said semiconductor substrate.  
     
     
         12 . The method as claimed in  claim 8 , further filling said isolation trenches with fourth isolation layers.  
     
     
         13 . The method as claimed in  claim 12 , wherein said fourth isolation layers are oxide layers.