Execution of instructions that lock and unlock computer resources

Abstract

When an atomic instruction executed by a computer processor locks a memory location, the locking is performed before the processor has determined whether the instruction is to be executed to completion or canceled. The memory location is unlocked whether or not the instruction will be canceled. Since the locking operation can occur before it is known whether the instruction will be canceled, the reading of the memory location can also occur early, before it is known whether the instruction will be canceled.

What is claimed is:  
     
         1 . A computer processor capable to execute a computer instruction which locks and then unlocks a computer resource, the computer processor being operable to lock the resource in the course of execution of the instruction before the processor has determined whether the instruction is to be executed to completion or canceled, the processor unlocking the resource by the time the instruction processing by the processor is terminated, the unlocking being performed whether or not the instruction is canceled.  
     
     
         2 . The computer processor of  claim 1  wherein the instruction execution is pipelined, and the instruction is canceled if a trap condition occurs after the processor started processing the instruction.  
     
     
         3 . The computer processor of  claim 1  wherein: 
 executing the instruction comprises reading a memory location and conditionally or unconditionally writing a memory location; and  
 the resource comprises the memory location to be written.  
 
     
     
         4 . The computer processor of  claim 3  further comprising a cache, wherein the memory location to be written is a memory location in said cache.  
     
     
         5 . The computer processor of  claim 3  wherein the circuitry is operable to perform the reading before the processor has determined whether the instruction is to be canceled.  
     
     
         6 . The processor of  claim 1  in combination with another processor having access to the same resource.  
     
     
         7 . The processor of  claim 1  wherein instruction execution is pipelined, and 
 if the processor determines before a pipeline stage of stages in which the unlocking is performed that the instruction is to be canceled, the instruction proceeds through all the pipeline stages at least up to, and including, the stage or stages in which the resource is unlocked.  
 
     
     
         8 . The processor of  claim 1  wherein: 
 each instruction is executed in a plurality of pipeline stages, wherein the pipeline for each instruction includes a stage ST1 in which a signal is generated by the processor to indicate whether the instruction is to be canceled due to a trap; and  
 when executing the instruction which locks and then unlocks the computer resource, the processor is operable to lock the computer resource before the stage ST1.  
 
     
     
         9 . The processor of  claim 8  wherein for at least some instructions including the instruction that locks and then locks the computer resource, the stage ST1 is followed by a stage ST2 in which at least one instruction result is written to an architecture storage location; and 
 when the processor executes the instruction that locks and then unlocks the computer resource, and the instruction is to be canceled, the stage ST2 is executed for the instruction to unlock the resource but writing to the architecture storage location is suppressed.  
 
     
     
         10 . A computer processor comprising an interface to a cache, the interface comprising: 
 address and data terminals; and    one or more control terminals to lock and unlock at least a portion of the cache, the one or more control terminals being operable to indicate that the cache is not to store data but to perform an unlock operation.    
     
     
         11 . The processor of  claim 10  in combination with said cache, the cache being connected to the address and data terminals and to the one or more control terminals.  
     
     
         12 . The combination of  claim 11  further comprising a second processor having data and address terminals and one or more control terminals, wherein said terminals of the second processor are connected to the cache.  
     
     
         13 . The combination of  claim 12  further comprising a memory and a circuit for caching data from the memory in the cache.  
     
     
         14 . A method for executing a computer instruction by a computer processor, wherein the instruction locks and then unlocks a computer resource, the method comprising: 
 locking the resource before the processor has determined whether the instruction is to be executed to completion or canceled; and then    unlocking the resource by the time the instruction processing by the processor is terminated, wherein the unlocking is performed whether or not the instruction is canceled.    
     
     
         15 . The method of  claim 14  wherein the unlocking is performed after the processor has determined whether the instruction is to be canceled.  
     
     
         16 . The method of  claim 14  wherein the instruction execution is pipelined, and the instruction is canceled if a trap condition occurs after the instructions processing by the processor has begun.  
     
     
         17 . The method of  claim 14  wherein the instruction is an atomic instruction which comprises reading a memory location and conditionally or unconditionally writing a memory location; and 
 the resource comprises the memory location to be written.  
 
     
     
         18 . The method of  claim 17  wherein the memory location to be written is a cache memory location.  
     
     
         19 . The method of  claim 17  wherein the reading operation is performed before the processor has determined whether the instruction is to be canceled.