A data buffer

Abstract

A direct memory access (DMA) first-in-first-out (FIFO) buffer includes two FIFO devices connected in parallel. An output multiplexer is controlled by a controller to pass to its output data provided by a selected one of the FIFO devices. Data is clocked into one FIFO device until it is full, after which data may be written from it. When data is written from a FIFO device, the FIFO device is emptied before data is again read into it. Using this arrangement, data can be read into one FIFO device whilst data is written from the other FIFO device.

What is claimed is:  
     
         1 . A data buffer comprising a signal input path, a signal output path, a multiplexer and first and second FIFO devices, wherein a data input of each of the FIFO devices is connected to the signal input path, an output of the multiplexer is connected to the signal output path, and a data output of each of the FIFO devices is connected to a respective data input of the multiplexer.  
     
     
         2 . A data buffer according to  claim 1 , further comprising a controller arranged to control switching of the multiplexer and to cause the FIFO devices to perform read operations and write operations.  
     
     
         3 . A data buffer according to  claim 2 , wherein the controller is arranged to detect full flags of the FIFO devices, the fall flags being set only when the respective FIFO device is fill of data, and to cause the FIFO devices to write data only in response to detection of their respective full flag being set.  
     
     
         4 . A data buffer according to  claim 3 , wherein the controller is arranged to cause the FIFO devices to write all of their data in a single data burst in response to detection of their respective full flag being set.  
     
     
         5 . A data buffer according to  claim 2 , wherein the controller is arranged to detect empty flags of the FIFO devices, the empty flags being set only when the respective FIFO device is empty of data, and to cause the FIFO devices to read data only in response to detection of their respective empty flags being set.  
     
     
         6 . A data buffer according to  claim 5 , wherein the controller is arranged to cause the FIFO devices to read data until they are full, in response to detection of their respective empty flags being set.  
     
     
         7 . A data buffer according to  claim 1 , further comprising first and second input/outputs connected to respective data inputs of a second multiplexer, the second multiplexer being controllable to alternately connect its inputs to the signal input path.  
     
     
         8 . A data buffer according to  claim 7 , wherein each of the first and second input/outputs is connected to its respective input of the second multiplexer via a respective clocked latch.  
     
     
         9 . A data buffer according to  claim 1 , the data buffer comprising first and second input/outputs, wherein the output of the first multiplexer is connected to the first input/output via a first switch and is connected to the second input/output via a second switch.  
     
     
         10 . A data buffer according to  claim 9 , wherein the input/outputs are connected to the signal output path via at least one clocked latch.  
     
     
         11 . An interface converter including a data buffer according to  claim 1.