Virtual gate design for thin packages

Abstract

The mold for a thin package uses a gate which has a high aspect ratio, e.g. about 30 degrees or greater throughout the length of the gate. Additionally, the depth of the gate goes to zero at a point outside of the area of the finished package, but within the dam bars, so that the leadframe space acts as a virtual gate. This reduces the need for trimming and lowers stress on the finished package.

What is claimed is:  
     
         1 . An encapsulated chip, comprising: 
 an integrated circuit chip;    leads to which said integrated circuit chip is bonded electrically;    an encapsulation material which encloses said integrated circuit chip and a portion of said leads, said encapsulation material having no trim marks.    
     
     
         2 . The encapsulated chip of  claim 1 , wherein said encapsulation material contains hardeners.  
     
     
         3 . A mold for chip encapsulation, comprising: 
 first and second mold halves;    said first mold half having 
 a first cavity for forming approximately one half of an encapsulated package and for containing a leadframe;  
   said second mold half having 
 a second cavity for forming approximately one half of an encapsulated package;  
 a runner cavity for directing molten encapsulant toward said first and second cavities;  
 a gate pin having a gate cavity for directing molten encapsulant between said runner cavity and said first and second cavities,  
   wherein said gate cavity has a depth which goes to zero at or before said first and second cavities.    
     
     
         4 . The mold of  claim 3 , wherein said mold is a chase mold.  
     
     
         5 . A gate pin for a mold for chip encapsulation, said gate pin comprising a channel for directing molten encapsulant between a runner and a package cavity, wherein said channel has a depth which goes to zero at or before an intersection with said package cavity.  
     
     
         6 . A method of encapsulating an integrated circuit chip, comprising the steps of: 
 placing a leadframe containing an integrated circuit chip within a mold;    routing molten encapsulation material into said mold through a gate whose depth goes to zero outside of the space occupied by the finished package.    
     
     
         7 . The method of  claim 6 , further comprising the steps of: 
 cooling said mold;    removing said leadframe from said mold;    removing encapsulant which cooled in said gate in a dejunking step.    
     
     
         8 . A method of encapsulating an integrated circuit chip, comprising the steps of: 
 placing a leadframe containing an integrated circuit chip within a mold;    routing molten encapsulation material into said mold through a gate whose angle of convergence with said leadframe is greater than about 30 degrees.