Methods of testing integrated circuitry, methods of forming tester substrates, and circuitry testing substrates

Abstract

A method of testing integrated circuitry includes providing a substrate comprising integrated circuitry to be tested. The circuitry substrate to be tested has a plurality of exposed conductors in electrical connection with the integrated circuitry. In one implementation, at least some of the exposed conductors of the circuitry substrate are heated to a temperature greater than 125° C. and within at least 50% in degrees centigrade of and below the melting temperature of the exposed conductors of the circuitry substrate. In one implementation, such are heated to a temperature below their melting temperature yet effective to soften said at least some of the exposed conductors to a point enabling their deformation upon application of less than or equal to 30 grams of pressure per exposed conductor. The circuitry substrate is engaged with a tester substrate. The tester substrate has a plurality of exposed conductors at least some of which are positioned to align with exposed conductors of the circuitry substrate. The engaging occurs while the at least some conductors of the circuitry substrate are heated to temperature and comprises contacting at least some of the exposed conductors of the tester substrate with conductors of the circuitry substrate. The integrated circuitry is tested through said conductors of the circuitry substrate and the tester substrate. Methods of forming tester substrates are disclosed, as are circuitry testing substrates.

1 . A method of testing integrated circuitry comprising: 
 engaging a conductive bump of a bumped circuit with an opening of a conductive receptacle at least partially formed in a surface of a test substrate;    heating at least a portion of the receptacle to deform the bump and be received more fully within the receptacle than initially so received by the engaging;    testing the bumped circuit through the bump deformed within the receptacle; and    after the testing, removing the bump from the receptacle.    
     
     
         2 . The method of  claim 1  wherein the heating is to a temperature greater than 125° C.  
     
     
         3 . The method of  claim 1  wherein the heating is to a temperature within at least 30% in degrees centigrade of the melting temperature of the conductive bump.  
     
     
         4 . The method of  claim 1  wherein the heating is to temperature within at least 20% in degrees centigrade of the melting temperature of the conductive bump.  
     
     
         5 . The method of  claim 1  wherein the heating is to a temperature not within less than 10% in degrees centigrade of the melting temperature of the conductive bump.  
     
     
         6 . The method of  claim 1  wherein the testing occurs after lowering temperature of the receptacle from its maximum bump deforming temperature.  
     
     
         7 . A method of testing integrated circuitry comprising: 
 providing a substrate comprising integrated circuitry to be tested, the circuitry substrate having a plurality of exposed conductors in electrical connection with the integrated circuitry;    heating at least some of the exposed conductors of the circuitry substrate to a temperature greater than 125° C. and within at least 50% in degrees centigrade of and below the melting temperature of the exposed conductors of the circuitry substrate;    engaging the circuitry substrate with a tester substrate, the tester substrate having a plurality of exposed conductors at least some of which are positioned to align with exposed conductors of the circuitry substrate, the engaging occurring while the at least some conductors of the circuitry substrate are heated to the temperature and comprising contacting at least some of the exposed conductors of the tester substrate with conductors of the circuitry substrate; and    testing the integrated circuitry through said conductors of the circuitry substrate and the tester substrate.    
     
     
         8 . The method of  claim 7  wherein the exposed conductors of the circuitry substrate comprise ball bumps.  
     
     
         9 . The method of  claim 8  wherein the pitch of the two closest of said ball bumps is less than 0.6 mm.  
     
     
         10 . The method of  claim 7  wherein the temperature is within at least 30% in degrees centigrade of the melting temperature of the exposed conductors of the circuitry substrate.  
     
     
         11 . The method of  claim 7  wherein the temperature is within at least 20% in degrees centigrade of the melting temperature of the exposed conductors of the circuitry substrate.  
     
     
         12 . The method of  claim 7  wherein the temperature is not within less than 10% in degrees centigrade of the melting temperature of the exposed conductors of the circuitry substrate.  
     
     
         13 . The method of  claim 7  wherein the heating to the temperature occurs prior to contact of any exposed conductor of the circuitry substrate with any exposed conductor of the tester substrate.  
     
     
         14 . The method of  claim 7  wherein the heating to the temperature occurs after contact of and while contacting at least one exposed conductor of the circuitry substrate with at least one exposed conductor of the tester substrate.  
     
     
         15 . The method of  claim 7  wherein the testing occurs after lowering temperature of the at least some conductors of the circuitry substrate from said temperature to a lower temperature.  
     
     
         16 . The method of  claim 7  wherein the testing occurs after lowering temperature of the at least some conductors of the circuitry substrate from said temperature to a lower temperature at least 20° C. lower than said temperature.  
     
     
         17 . The method of  claim 7  wherein the testing occurs after lowering temperature of the at least some conductors of the circuitry substrate from said temperature to a lower temperature at least 100° C. lower than said temperature.  
     
     
         18 . The method of  claim 7  wherein the testing occurs after lowering temperature of the at least some conductors of the circuitry substrate from said temperature to a lower temperature at or below 125° C.  
     
     
         19 . The method of  claim 7  wherein the exposed conductors of the tester substrate comprise receptacles within which at least some of the exposed conductors of the circuitry substrate are received during the engaging.  
     
     
         20 . The method -of  claim 7  wherein the exposed conductors of the tester substrate comprise indentations formed into an outer surface of the tester substrate, the engaging comprising positioning at least some of the plurality of exposed conductors of the circuitry substrate within the tester substrate indentations.  
     
     
         21 . The method of  claim 7  wherein the engaging starts by contacting less than all exposed conductors of the circuitry substrate with the exposed conductors of the tester substrate, and the heating to said temperature of individual exposed conductors of the circuitry substrate occurs after contact of respective individual of the exposed conductors of the circuitry substrate with individual tester substrate exposed conductors.  
     
     
         22 . The method of  claim 7  wherein the exposed conductors of the tester substrate comprise indentations formed into an outer surface of the tester substrate, the heating comprising heating the indentations at least to said temperature and heating individual exposed conductors to said temperature resulting from contact of respective individual of the exposed conductors of the circuitry substrate with the heated indentations.  
     
     
         23 . A method of testing integrated circuitry comprising: 
 providing a substrate comprising integrated circuitry to be tested, the circuitry substrate having a plurality of exposed conductors in electrical connection with the integrated circuitry;    heating at least some of the exposed conductors of the circuitry substrate to a temperature below their melting temperature yet effective to soften said at least some of the exposed conductors to a point enabling their deformation upon application of less than or equal to 30 grams of pressure per exposed conductor;    engaging the circuitry substrate with a tester substrate, the tester substrate having a plurality of exposed conductors at least some of which are positioned to align with the exposed conductors of the circuitry substrate, the engaging occurring while the at least some conductors of the circuitry substrate are heated to the temperature and comprising contacting at least some of the exposed conductors of the tester substrate with conductors of the circuitry substrate; and    testing the integrated circuitry through said conductors of the circuitry substrate and the tester substrate.    
     
     
         24 . The method of  claim 23  wherein the temperature is within at least 30% in degrees centigrade of the melting temperature of the exposed conductors of the circuitry substrate.  
     
     
         25 . The method of  claim 23  wherein the temperature is within at least 20% in degrees centigrade of the melting temperature of the exposed conductors of the circuitry substrate.  
     
     
         26 . The method of  claim 23  wherein the temperature is not within less than 10% in degrees centigrade of the melting temperature of the exposed conductors of the circuitry substrate.  
     
     
         27 . The method of  claim 23  wherein the heating to the temperature occurs after contact of and while contacting at least one exposed conductor of the circuitry substrate with at least one exposed conductor of the tester substrate.  
     
     
         28 . The method of  claim 23  wherein the testing occurs after lowering temperature of the at least some conductors of the circuitry substrate from said temperature to a lower temperature.  
     
     
         29 . The method of  claim 23  wherein the exposed conductors of the tester substrate comprise indentations formed into an outer surface of the tester substrate, the engaging comprising positioning at least some of the plurality of exposed conductors of the circuitry substrate within the tester substrate indentations.  
     
     
         30 . A method of forming a tester substrate for testing circuitry having a plurality of exposed conductors, the method comprising: 
 forming a plurality of conductive receptacles at least partially received into a surface of a substrate, the receptacles being sized to receive one of the plurality of exposed conductors of circuitry being tested; and    forming a resistive receptacle heating element supported by the substrate proximate at least a portion of at least some of the conductive receptacles.    
     
     
         31 . The method of  claim 30  wherein at least a portion of respective conductive receptacles is formed prior to forming the respective heating elements.  
     
     
         32 . The method of  claim 30  wherein at least a portion of respective conductive receptacles is formed after forming the respective heating elements.  
     
     
         33 . The method of  claim 30  comprising forming a portion of the respective receptacles to overlie a portion of the respective heating elements.  
     
     
         34 . A method of forming a tester substrate for testing circuitry having a plurality of exposed conductors, the method comprising: 
 forming a plurality of conductive receptacles at least partially received into a surface of a substrate, the receptacles being sized to receive one of the plurality of exposed conductors of circuitry being tested and comprising a periphery; and    lining at least some of the conductive receptacles with a resistive receptacle heating element received proximate at least a portion of the respective receptacle periphery.    
     
     
         35 . The method of  claim 34  wherein the resistive receptacle heating element lines only a portion of the respective receptacle periphery.  
     
     
         36 . The method of  claim 34  wherein at least a portion of respective conductive receptacles is formed prior to forming the respective heating elements.  
     
     
         37 . The method of  claim 34  wherein at least a portion of respective conductive receptacles is formed after forming the respective heating elements.  
     
     
         38 . The method of  claim 34  comprising forming a portion of the respective receptacles to overlie a portion of the respective heating elements.  
     
     
         39 . The method of  claim 34  comprising forming the resistive heating elements to be spaced and electrically isolated from the conductive receptacles.  
     
     
         40 . A circuitry testing substrate comprising: 
 an outer substrate surface having a plurality of conductive receptacles formed into said surface; and    resistive receptacle heating elements supported by the substrate and being received proximate the conductive receptacles, and being spaced from conductive portions of the conductive receptacles.    
     
     
         41 . The circuitry testing substrate of  claim 40  wherein at least a portion of the respective conductive receptacles overlie the resistive heating elements.  
     
     
         42 . The circuitry testing substrate of  claim 40  wherein the respective conductive receptacles have a respective periphery, the respective heating element being received about only portion of the respective periphery.  
     
     
         43 . The circuitry testing substrate of  claim 40  wherein, 
 at least a portion of the respective conductive receptacles overlie the resistive heating elements; and  
 the respective conductive receptacles have a respective periphery, the respective heating element being received about only portion of the respective periphery.  
 
     
     
         44 . A circuitry testing substrate comprising: 
 an outer substrate surface having a plurality of conductive receptacles formed into said surface; and    means supported by the substrate for heating the conductive receptacles.    
     
     
         45 . The circuitry testing substrate of  claim 44  wherein the means comprises a resistive heating element.  
     
     
         46 . The circuitry testing substrate of  claim 45  wherein the resistive heating element comprises conductively doped polysilicon.  
     
     
         47 . The circuitry testing substrate of  claim 45  wherein at least a portion of the means underlies at least a portion of the receptacles.  
     
     
         48 . The circuitry testing substrate of  claim 45  wherein the means does not comprise the conductive receptacles.  
     
     
         49 . The circuitry testing substrate of  claim 45  wherein the means are at least partially formed by photolithographic patterning of a conductive layer formed over the substrate.  
     
     
         50 . The circuitry testing substrate of  claim 49  wherein the conductive layer comprises conductively doped semiconductive material.  
     
     
         51 . The circuitry testing substrate of  claim 49  wherein the conductive layer consists essentially of conductively doped semiconductive material.