Non-volatile semiconductor memory device

Abstract

The present invention relates to a method of forming a non-volatile memory device such as an EEPROM device. The non-volatile memory device is formed of an array of memory cells ( 10 ) organized into rows ( 20 ) and columns ( 22 ) within a semiconductor substrate ( 100 ). Each cell ( 10 ) comprises a gate structure ( 120 ) formed of a first dielectric layer ( 122 ), a floating gate ( 124 ), a second dielectric layer ( 126 ) and a control gate ( 128 ) formed in a well ( 50 ). The memory device further comprises insulating trenches ( 200 ) formed in said substrate ( 100 ) along a direction parallel to said columns ( 22 ) and isolating each cell ( 10 ) within a column ( 22 ) from other cells ( 10 ) within adjacent columns ( 22 ). FIG. 3, 3 a , 3 b

What is claimed is  
     
         1 . A method of forming a non-volatile semiconductor memory device, said device being formed of an array of memory cells organized into rows and columns within a semiconductor substrate, wherein the method comprises the steps of: 
 a) performing a blanket implant in the semiconductor substrate resulting in the formation of a uniformly doped region;    b) forming insulating trenches in said semiconductor substratein a direction parallel to said columns;    c) forming wellsin said substrate between said insulating trenches, so as to define alternated source and drain regions along said columns, each of said wells having a bottom surface and having first and second pairs of facing sidewalls being respectively adjacent to said source and drain regions and to said insulating trenches;    d) forming a first dielectric layer over the surface of said substrate and said wells;    e) forming a first conductive layer over said first dielectric layer;    f) removing portions of said first conductive layer, so as to define strips overlying said wells in a direction parallel to said columns;    g) forming a second dielectric layer over said first conductive layer;    h) forming a second conductive layer over said second dielectric layer; and    i) removing portions of said first and second conductive layers and said second dielectric layer, so as to define gate structures overlying said wells along said rows.    
     
     
         2 . A method according to  claim 1 , wherein it further comprises, directly following the formation of said wells according to step c), the steps of: 
 aa) forming a thin layer of oxide over the surface of said wells;    bb) performing a high temperature annealling process; and    cc) stripping said thin layer of oxide.    
     
     
         3 . A method according to  claim 1  or  2 , wherein said insulating trenches are interrupted at periodic intervals so that the source regions of the memory cell form a common source line.  
     
     
         4 . A non-volatile memory device formed of an array of memory cells organized into rows and columns, each of said cells comprising source, drain and channel formed in a semiconductor substrate and a gate structure overlying said channel and comprising a first dielectric layer, a floating gate, a second dielectric layer and a control gate, wherein each of said cells is formed in a well, said memory device further comprising insulating trenches formed in said substrate along a direction parallel to said columns and isolating each cell within a column from other cells within adjacent columns.  
     
     
         5 . A non-volatile memory device according to  claim 4 , wherein said insulating trenches are interrupted at periodic intervals so that the source regions of the memory cells form a common source line.