Electrode resistance improved MOSFET with source and drain regions reduced in size beyond lithography limit and method for making the same

Abstract

A MOSFET whose source and drain regions are reduced in size beyond lithography limit is improved with a reduction of electrode contact resistance by forming a silicide on the gate electrode layer and the source and drain regions thereof. In a method for making the MOSFET, a sacrificial layer is formed in stack on a gate electrode layer of a silicon rich material before source and drain regions are implanted or diffused with the sacrificial layer and gate electrode layer as a mask, an insulator spacer is then formed on sidewalls of the gate electrode layer and the sacrificial layer so that a trench is formed on the gate electrode layer and surrounded by the spacer in the subsequent process when the sacrificial layer is removed, a metal is deposited in the trench and on the source and drain regions with a portion extending to an isolation region which surrounds the MOSFET and practiced with a heat treatment to form a silicide on the gate electrode layer and the source and drain regions, and finally a dielectric layer is deposited on the metal in which contact holes are then formed and a conductive material is filled into the contact holes to reach the metal.

What is claimed is:  
     
         1 . A method for making a MOSFET in an active region surrounded by an isolation region in a surface of a silicon substrate, said method comprising the steps of: 
 forming a gate oxide on said active region;    selectively forming a gate electrode layer of a silicon rich material and a sacrificial layer in stack on said gate oxide;    forming source and drain regions in said active region with said gate electrode and sacrificial layers as a mask;    selectively removing a portion of said gate oxide on said source and drain regions;    forming an insulator spacer on sidewalls of said gate electrode and sacrificial layers;    removing said sacrificial layer in result with a trench formed on said gate electrode layer and surrounded by said spacer;    depositing a metal layer in said trench and on said source and drain regions partially extending to a surface of said isolation region;    forming a silicide on said gate electrode layer and source and drain regions with use of said metal and gate electrode layers;    forming a dielectric layer on said metal layer;    forming contact holes in said dielectric layer extending to said metal layer; and    filling a conductive material in said contact holes reaching said metal layer.    
     
     
         2 . A method according to  claim 1 , wherein said gate electrode layer is formed of polycrystalline silicon.  
     
     
         3 . A method according to  claim 1 , wherein said sacrificial layer is formed of silicon nitride.  
     
     
         4 . A method according to  claim 1 , wherein said spacer is formed of thermal or CVD silicon dioxide.  
     
     
         5 . A method according to  claim 1 , wherein said metal layer is formed of CVD tungsten.  
     
     
         6 . A method according to  claim 1 , wherein said silicide is formed by heat treatment.  
     
     
         7 . A method according to  claim 1 , wherein said sacrificial layer is removed by a high selectivity etch.  
     
     
         8 . A method for making a MOSFET in an active region surrounded by an isolation region in a surface of a silicon substrate, said method comprising the steps of: 
 forming a gate oxide on said active region;    selectively forming a gate electrode layer of a silicon rich material and a sacrificial layer in stack on said gate oxide;    forming source and drain regions in said active region with said gate electrode and sacrificial layers as a mask;    selectively removing a portion of said gate oxide on said source and drain regions;    forming an insulator spacer on sidewalls of said gate electrode and sacrificial layers;    removing said sacrificial layer in result with a trench formed on said gate electrode layer and surrounded by said spacer;    depositing a metal layer in said trench and on said source and drain regions;    forming a silicide on said gate electrode layer and source and drain regions with use of said metal and gate electrode layers;    depositing a conductive layer on said metal layer on said source and drain regions partially extending to a surface of said isolation region;    forming a dielectric layer on said conductive layer;    forming contact holes in said conductive layer extending to a surface of said conductive layer; and    filling a conductive material in said contact holes reaching said conductive layer.    
     
     
         9 . A method according to  claim 8 , wherein said gate electrode layer is formed of polycrystalline silicon.  
     
     
         10 . A method according to  claim 8 , wherein said sacrificial layer is formed of silicon nitride.  
     
     
         11 . A method according to  claim 8 , wherein said spacer is formed of thermal or CVD silicon dioxide.  
     
     
         12 . A method according to  claim 8 , wherein said metal layer is formed of CVD tungsten.  
     
     
         13 . A method according to  claim 8 , wherein said silicide is formed by heat treatment.  
     
     
         14 . A method according to  claim 8 , wherein said sacrificial layer is removed by a high selectivity etch.  
     
     
         15 . A method according to  claim 8 , further comprising etching back said metal layer for removing said metal layer on said spacer and leaving a portion of said metal layer in said trench and on said source and drain regions after depositing said metal layer.  
     
     
         16 . A method according to  claim 8 , further comprising etching back said conductive layer for removing said conductive layer on said spacer and metal layer in the trench and leaving a portion of said conductive layer partially extending to said surface of said isolation region after depositing said conductive layer.  
     
     
         17 . A method for making a MOSFET in an active region surrounded by an isolation region in a surface of a silicon substrate, said method comprising the steps of: 
 forming a gate oxide on said active region;    selectively forming a gate electrode layer of a silicon rich material and a sacrificial layer in stack on said gate oxide;    selectively removing a portion of said gate oxide on said source and drain regions;    forming source and drain regions in said active region with said gate electrode and sacrificial layers as a mask;    forming an insulator spacer on sidewalls of said gate electrode and sacrificial layers;    removing said sacrificial layer in result with a trench formed on said gate electrode layer and surrounded by said spacer;    depositing a metal layer in said trench and on said source and drain regions partially extending to a surface of said isolation region;    forming a silicide on said gate electrode layer and source and drain regions with use of said metal and gate electrode layers;    forming a dielectric layer on said metal layer;    forming contact holes in said dielectric layer extending to said metal layer; and    filling a conductive material in said contact holes reaching said metal layer.    
     
     
         18 . A method according to  claim 17 , wherein said gate electrode layer is formed of polycrystalline silicon.  
     
     
         19 . A method according to  claim 17 , wherein said sacrificial layer is formed of silicon nitride.  
     
     
         20 . A method according to  claim 17 , wherein said spacer is formed of thermal or CVD silicon dioxide.  
     
     
         21 . A method according to  claim 17 , wherein said metal layer is formed of CVD tungsten.  
     
     
         22 . A method according to  claim 17 , wherein said silicide is formed by heat treatment.  
     
     
         23 . A method according to  claim 17 , wherein said sacrificial layer is removed by a high selectivity etch.  
     
     
         24 . A method for making a MOSFET in an active region surrounded by an isolation region in a surface of a silicon substrate, said method comprising the steps of: 
 forming a gate oxide on said active region;    selectively forming a gate electrode layer of a silicon rich material and a sacrificial layer in stack on said gate oxide;    forming source and drain regions in said active region with said gate electrode and sacrificial layers as a mask;    selectively removing a portion of said gate oxide on said source and drain regions;    forming an insulator spacer on sidewalls of said gate electrode and sacrificial layers;    removing said sacrificial layer in result with a trench formed on said gate electrode layer and surrounded by said spacer;    depositing a metal layer in said trench and on said source and drain regions;    forming a silicide on said gate electrode layer and source and drain regions with use of said metal and gate electrode layers;    depositing a conductive layer on said metal layer on said source and drain regions partially extending to a surface of said isolation region;    forming a dielectric layer on said conductive layer;    forming contact holes in said conductive layer extending to a surface of said conductive layer; and    filling a conductive material in said contact holes reaching said conductive layer.    
     
     
         25 . A method according to  claim 24 , wherein said gate electrode layer is formed of polycrystalline silicon.  
     
     
         26 . A method according to  claim 24 , wherein said sacrificial layer is formed of silicon nitride.  
     
     
         27 . A method according to  claim 24 , wherein said spacer is formed of thermal or CVD silicon dioxide.  
     
     
         28 . A method according to  claim 24 , wherein said metal layer is formed of CVD tungsten.  
     
     
         29 . A method according to  claim 24 , wherein said silicide is formed by heat treatment.  
     
     
         30 . A method according to  claim 24 , wherein said sacrificial layer is removed by a high selectivity etch.  
     
     
         31 . A method according to  claim 24 , further comprising etching back said metal layer for removing said metal layer on said spacer and leaving a portion of said metal layer in said trench and on said source and drain regions after depositing said metal layer.  
     
     
         32 . A method according to  claim 24 , further comprising etching back said conductive layer for removing said conductive layer on said spacer and metal layer in the trench and leaving a portion of said conductive layer partially extending to said surface of said isolation region after depositing said conductive layer.  
     
     
         33 . A MOSFET structure in an active region surrounded by an isolation region in a surface of a silicon substrate, said structure comprising: 
 source and drain regions in said active region with a channel region between said source and drain regions;    a gate electrode layer above said channel region with a gate oxide therebetween;    silicide layers on said gate electrode layer and source and drain regions;    an insulator spacer on sidewalls of said gate electrode and silicide on said gate electrode layer;    conductive layers extending from said silicide on source and drain regions to a surface of said isolation region;    a dielectric layer on said conductive layer;    contact holes in said dielectric layer extending to said conductive layer; and    a conductive material in said contact holes reaching said conductive layer.    
     
     
         34 . A structure according to  claim 33 , wherein said gate electrode layer comprises a polycrystalline silicon.  
     
     
         35 . A structure according to  claim 33 , wherein said spacer comprises a thermal or CVD silicon dioxide.  
     
     
         36 . A structure according to  claim 33 , wherein said silicide layers are tungsten silicide layers.  
     
     
         37 . A structure according to  claim 33 , wherein said source and drain regions are impurity diffused regions.  
     
     
         38 . A structure according to  claim 33 , wherein said conductive layers are CVD tungsten layers.  
     
     
         39 . A structure according to  claim 33 , wherein said silicide layer on said gate electrode layer is formed in a trench surrounded by said spacer.