Heterostructure thermionic coolers
Abstract
A heterostructure thermionic cooler and a method for making thermionic coolers, employing a barrier layer of varying conduction bandedge for n-type material, or varying valence bandedge for p-type material, that is placed between two layers of material. The barrier layer has a high enough barrier for the cold side to only allow “hot” electrons, or electrons of high enough energy, across the barrier. The barrier layer is constructed to have an internal electric field such that the electrons that make it over the initial barrier are assisted in travel to the anode. Once electrons drop to the energy level of the anode, they lose energy to the lattice, thus heating the lattice at the anode. The barrier height of the barrier layer is high enough to prevent the electrons from traveling in the reverse direction.
Claims
exact text as granted — not AI-modifiedWhat is claimed is:
1 . A method for making a thermionic non-isothermal device, comprising the steps of:
growing a semiconductor layer with a first bandedge; and growing a first barrier layer on the semiconductor layer, wherein the first barrier layer has a higher bandedge than the bandedge of the semiconductor layer.
2 . The method of claim 1 , the method further comprising the step of growing a second semiconductor layer on the first barrier layer.
3 . The method of claim 2 , wherein the method further comprises the step of growing at least one additional barrier layer on the second semiconductor layer.
4 . The method of claim 3 , wherein the method further comprises the step of growing at least one additional semiconductor layer on the additional barrier layer.
5 . The method of claim 3 , wherein the method further comprises the step of growing at least one additional pair of alternating barrier layers and semiconductor layers on the second semiconductor layer.
6 . The method of claim 1 , wherein the method further comprises the step of growing at least one additional barrier layer on the first barrier layer.
7 . The method of claim 1 , wherein a thickness of the second semiconductor layer is between 0.01 and 1 micron.
8 . The method of claim 1 , wherein the first semiconductor layer is selected from a group comprising gallium arsenide, indium phosphide, silicon, silicon germanium, lead telluride, indium gallium arsenide (In x Ga 1-x As), indium arsenide (InAs), indium antimonide (InSb), indium gallium arsenide antimonide (In x Ga 1-x As y Sb 1-y ), mercury cadmium telluride (Hg x Cd 1-x Te), mercury cadmium selenide (Hg x Cd 1-x Se), gallium nitride (GaN), aluminum gallium nitride (Al x Ga 1-x N), indium gallium nitride (In x Ga 1-x N), indium arsenide phosphide (InAs y P 1-y ) indium gallium arsenide phosphide (In x Ga 1-x As y P 1-y ), indium gallium aluminum arsenide (In x Ga y Al 1-x-y As), lead tin telluride (Pb x Sn 1-x Te), aluminum arsenide (AlAs), aluminum antimonide (AlSb), zinc selenide (ZnSe), zinc telluride (ZnTe), boron nitride (BN), germanium (Ge), gallium phosphide (GaP), gallium antimonide (GaSb), gallium aluminum arsenide (Ga x Al 1-x As), gallium arsenide phosphide (GaAs y P 1-y ), gallium indium phosphide (Ga x In 1-x P), and gallium indium antimonide (Ga x In 1-x Sb), bismuth telluride (Bi 2 Te 3 ), and bismuth selenide (Bi 2 Se 3 ), where the subscripts x, y, 1 -x, and 1 -y denote the relative amounts of the atomic species in each ternary or quartenary materials and range from zero to one, inclusive.
9 . The method of claim 1 , wherein the second semiconductor layer is selected from a group comprising aluminum gallium arsenide, indium gallium arsenide phosphide, silicon germanium, lead europium telluride, silicon oxide, aluminum oxide, vacuum, mercury cadmium telluride, mercury cadmium selenide, indium gallium arsenide antimonide, indium gallium aluminum nitride, bismuth telluride, bismuth selenide, boron nitride, zinc telluride, zinc selenide, lead tin telluride, aluminum antimonide, lead telluride, and air.
10 . The method of claim 1 , wherein the third semiconductor layer is the same material as the first semiconductor layer.
11 . The method of claim 1 , wherein the bandedge of the second semiconductor layer is piecewise linear.
12 . The method of claim 1 , wherein the bandedge of the second semiconductor layer is monotonically increasing.
13 . The method of claim 1 , wherein the bandedge of the second semiconductor is a step function.
14 . The method of claim 1 , wherein the method further comprises selectively removing a portion of the second semiconductor layer.
15 . The method of claim 1 , wherein the first semiconductor layer is n-type, and the bandedge is a conduction bandedge.
16 . The method of claim 11 wherein the first semiconductor layer is p-type, and the bandedge is a valence bandedge.
17 . The method of claim 1 , wherein the second layer is a strained layer.
18 . The method of claim 1 , wherein the second layer is selectively oxidized.
19 . A non-isothermal thermionic device, comprising:
a semiconductor layer with a first bandedge; and a first barrier layer attached to the semiconductor layer, wherein the first barrier layer has a higher bandedge than the bandedge of the semiconductor layer.
20 . The non-isothermal thermionic device of claim 19 , further comprising a second semiconductor layer attached to the first barrier layer.
21 . The non-isothermal thermionic device of claim 20 , further comprising at least one additional barrier layer attached to the second semiconductor layer.
22 . The non-isothermal thermionic device of claim 21 , further comprising at least one additional semiconductor layer attached to the additional barrier layer.
23 . The non-isothermal thermionic device of claim 20 , further comprising at least one additional pair of alternating barrier layers and semiconductor layers attached to the second semiconductor layer.
24 . The non-isothermal thermionic device of claim 19 , further comprising at least one additional barrier layer attached to the first barrier layer.
25 . The non-isothermal thermionic device of claim 19 , wherein a thickness of the second semiconductor layer is between 0.01 and 1 micron.
26 . The non-isothermal thermionic device of claim 19 , wherein the first semiconductor layer is selected from a group comprising gallium arsenide, indium phosphide, silicon, silicon germanium, lead telluride, indium gallium arsenide (In x Ga 1-x As), indium arsenide (InAs), indium antimonide (InSb), indium gallium arsenide antimonide (In x Ga 1-x As y Sb 1-y ), mercury cadmium telluride (Hg x Cd 1-x Te), mercury cadmium selenide (Hg x Cd 1-x Se), gallium nitride (GaN), aluminum gallium nitride (Al x Ga 1-x N), indium gallium nitride (In x Ga 1-x N), indium arsenide phosphide (InAs y P 1-y ), indium gallium arsenide phosphide (In x Ga 1-x As y P 1-y ), indium gallium aluminum arsenide (In x Ga 1-x-y As), lead tin telluride (Pb x Sn 1-x Te), aluminum arsenide (AlAs), aluminum antimonide (AlSb), zinc selenide (ZnSe), zinc telluride (ZnTe), boron nitride (BN), germanium (Ge), gallium phosphide (GaP), gallium antimonide (GaSb), gallium aluminum arsenide (Ga x Al 1-x As), gallium arsenide phosphide (GaAs y P 1-y ), gallium indium phosphide (Ga x In 1-x P) gallium indium antimonide (Ga x In 1-x Sb), bismuth telluride (Bi 2 Te 3 ), and bismuth selenide (Bi 2 Se 3 ), where the subscripts x, y, 1 -x, and 1 -y denote the relative amounts of the atomic species in each ternary or quartenary materials and range from zero to one, inclusive.
27 . The non-isothermal thermionic device of claim 19 , wherein the second semiconductor layer is selected from a group comprising aluminum gallium arsenide, indium gallium arsenide phosphide, silicon germanium, lead europium telluride, silicon oxide, aluminum oxide, vacuum, mercury cadmium telluride, mercury cadmium selenide, indium gallium arsenide antimonide, indium gallium aluminum nitride, bismuth telluride, bismuth selenide, boron nitride, zinc telluride, zinc selenide, lead tin telluride, aluminum antimonide, lead telluride, and air.
28 . The non-isothermal thermionic device of claim 19 , wherein the third semiconductor layer is the same material as the first semiconductor layer.
29 . The non-isothermal thermionic device of claim 19 , wherein the bandedge of the second semiconductor layer is piecewise linear.
30 . The non-isothermal thermionic device of claim 19 , wherein the bandedge of the second semiconductor layer is monotonically increasing.
31 . The non-isothermal thermionic device of claim 19 , wherein the bandedge of the second semiconductor is a step function.
32 . The non-isothermal thermionic device of claim 19 , wherein the second semiconductor layer is selectively removed.
33 . The non-isothermal thermionic device of claim 19 , wherein the first semiconductor layer is n-type, and the bandedge is a conduction bandedge.
34 . The non-isothermal thermionic device of claim 19 , wherein the first semiconductor layer is p-type, and the bandedge is a valence bandedge.
35 . A thermionic power generation device, comprising:
a semiconductor layer with a first bandedge; and a first barrier layer attached to the semiconductor layer, wherein the first barrier layer has a higher bandedge than the bandedge of the semiconductor layer.
36 . The thermionic power generation device of claim 35 , further comprising a second semiconductor layer attached to the first barrier layer.
37 . The thermionic power generation device of claim 36 , further comprising at least one additional barrier layer attached to the second semiconductor layer.
38 . The thermionic power generation device of claim 37 , further comprising at least one additional semiconductor layer attached to the additional barrier layer.
39 . The thermionic power generation device of claim 36 , further comprising at least one additional pair of alternating barrier layers and semiconductor layers attached to the second semiconductor layer.
40 . The thermionic power generation device of claim 35 , further comprising at least one additional barrier layer attached to the first barrier layer.
41 . The thermionic power generation device of claim 35 , wherein a thickness of the second semiconductor layer is between 0.01 and 1 micron.
42 . The thermionic power generation device of claim 35 , wherein the first semiconductor layer is selected from a group comprising gallium arsenide, indium phosphide, silicon, silicon germanium, lead telluride indium gallium arsenide (In x Ga 1-x As), indium arsenide (InAs), indium antimonide (InSb), indium gallium arsenide antimonide (In x Ga 1-x As y Sb 1-y ), mercury cadmium telluride (Hg x Cd 1-x Te) mercury cadmium selenide (Hg x Cd 1-x Se), gallium nitride (GaN), aluminum gallium nitride (Al x Ga 1-x N), indium gallium nitride (In x Ga 1-x N), indium arsenide phosphide (InAs y P 1-y ), indium gallium arsenide phosphide (In x Ga 1-x As y P 1-y ), indium gallium aluminum arsenide (In x Ga y Al 1-x-y As), lead tin telluride (Pb x Sn 1-x Te), aluminum arsenide (AlAs), aluminum antimonide (AlSb), zinc selenide (ZnSe), zinc telluride (ZnTe), boron nitride (BN), germanium (Ge), gallium phosphide (GaP), gallium antimonide (GaSb), gallium aluminum arsenide (Ga x Al 1-x As), gallium arsenide phosphide (GaAs y P 1-y ), gallium indium phosphide (Ga x In 1-x P), gallium indium antimonide (Ga x In 1-x Sb), bismuth telluride (Bi 2 Te 3 ), and bismuth selenide (Bi 2 Se 3 ), where the subscripts x, y, 1 -x, and 1 -y denote the relative amounts of the atomic species in each ternary or quartenary materials and range from zero to one, inclusive.
43 . The thermionic power generation device of claim 35 , wherein the second semiconductor layer is selected from a group comprising aluminum gallium arsenide, indium gallium arsenide phosphide, silicon germanium, lead europium telluride, silicon oxide, aluminum oxide, vacuum, mercury cadmium telluride, mercury cadmium selenide, indium gallium arsenide antimonide, indium gallium aluminum nitride, bismuth telluride, bismuth selenide, boron nitride, zinc telluride, zinc selenide, lead tin telluride, aluminum antimonide, lead telluride, and air.
44 . The thermionic power generation device of claim 35 , wherein the third semiconductor layer is the same material as the first semiconductor layer.
45 . The thermionic power generation device of claim 35 , wherein the bandedge of the second semiconductor layer is piecewise linear.
46 . The thermionic power generation device of claim 35 , wherein the bandedge of the second semiconductor layer is monotonically increasing.
47 . The thermionic power generation device of claim 35 , wherein the bandedge of the second semiconductor is a step function.
48 . The thermionic power generation device of claim 35 , wherein the second semiconductor layer is selectively removed.
49 . The thermionic power generation device of claim 35 , wherein the first semiconductor layer is n-type, and the bandedge is a conduction bandedge.
50 . The thermionic power generation device of claim 35 , wherein the first semiconductor layer is p-type, and the bandedge is a valence bandedge.
51 . The thermionic power generation device of claim 35 , wherein the second layer is selectively oxidized.
52 . The thermionic power generation device of claim 35 , wherein the thermionic power generation device is a pixel of an imaging system.
53 . The thermionic power generation device of claim 35 , wherein the thermionic power generation device forms more than one pixel of an imaging system.
54 . A method for making a thermionic non-isothermal device, comprising the steps of:
growing a metal layer with a Fermi energy; and growing a first barrier layer on the metal layer, wherein a conduction bandedge of the first barrier layer is higher than the Fermi energy of the metal layer.
55 . A thermionic non-isothermal device, comprising:
a metal layer with a Fermi energy; and a first barrier layer attached to the metal layer, wherein a conduction bandedge of the first barrier layer is higher than the Fermi energy of the metal layer.Join the waitlist — get patent alerts
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