Method for manipulating a stack pointer with post increment/decrement operation

Abstract

The stack pointer is used for generating the next unutilized location in the stack memory device in order to indicate where a current value in the program counter is to be written. The stack pointer also generates a directly preceding location to the next unutilized location in order to read the last value of the program counter that was written to the stack memory device. The stack pointer will select the next unutilized location in the stack memory device for a write operation and the directly preceding location to the next unutilized location in the stack memory device for a read operation. The stack pointer will further perform either a post increment or post decrement operation on the next unutilized location in the stack memory device after execution of a current instruction.

What is claimed is:  
     
         1 . A pre-decode stack pointer system with post revise operation comprising, in combination: 
 a stack memory device which stores and retrieves values of a program counter; and    a stack pointer coupled to said stack memory device for generating next unutilized location in said stack memory device to indicate where a current value of said program cbunter is to be written, for generating a directly preceding location to said next unutilized location to read a last value of said program counter written to said stack memory device, for selecting one of said next unutilized location in said stack memory device or said directly preceding location to said next unutilized location in said stack memory device, and for one of post incrementing or post decrementing said next unutilized location in said stack memory device after execution of a current instruction.    
     
     
         2 . A pre-decode stack pointer system with post revise operation in accordance with  claim 1  wherein said stack pointer comprises: 
 a selection circuit coupled to said stack memory device for selecting and outputting said one of said next unutilized location in said stack memory device or said directly preceding location to said next unutilized address location in said stack memory device;  
 a master latch coupled to said selection circuit for storing said next unutilized location in said stack memory device; and  
 an increment decrement circuit coupled to said selection circuit and to said master latch for pre-decrementing said next unutilized location in said stack memory device to generate said directly preceding location to said next unutilized location to read data from said last value of said program counter written to said stack memory device and for one of post incrementing said next unutilized location after execution of said current instruction to generate next available unutilized location in said stack memory device where a next value of said program counter is to be written or post decrementing said next unutilized location after execution of said current instruction to generate said directly preceding location to said unutilized location to read data from said last value of said program counter written to said stack memory device.  
 
     
     
         3 . A pre-decode pointer system with post revise operation in accordance with  claim 2  further comprising a slave latch circuit coupled to said master latch and to said increment decrement circuit for storing and sending to said master latch one of said next available unutilized location in said stack memory device where a next value of said program counter is to be written or said directly preceding location to said unutilized location to read data from said last value of said program counter written to said stack memory device.  
     
     
         4 . A pre-decode pointer system with post revise operation in accordance with  claim 2  wherein said selection means is a multiplexer circuit.  
     
     
         5 . A pre-decode pointer system with post revise operation comprising, in combination: 
 a memory device for storing and transferring address data; and    a pointer coupled to said memory device for generating a current location in said memory device where said address data is to be written, for generating a current location in said memory device where said address data is to be read, for selecting one of said current location in said memory device where said address data is to be written or said current location in said memory device where said address data is to be read, and for one of post incrementing or post decrementing said current location where said address data is to be written after execution of a current instruction.    
     
     
         6 . A pre-decode pointer system with post revise operation in accordance with  claim 5  wherein said pointer stores said address data in said memory device and reads said address data from said memory device on a first in last out (FILO) basis.  
     
     
         7 . A pre-decode pointer system with post revise operation in accordance with  claim 5  wherein said pointer comprises: 
 a selection circuit coupled to said memory device for selecting and outputting one of said current location in said memory device where said address data is to be written or said current location in said memory device where said address data is to be read;  
 a master latch coupled to said selection circuit for storing said current location in said memory device where said address data is to be written; and  
 an increment decrement circuit coupled to said selection circuit and to said master latch for pre-decrementing said current location in said memory device where said address data is to be written to generate a last location in said memory device where said address data was written to read said address data and for one of post incrementing said current location in said memory device after execution of a current instruction to generate next available location in said memory device where said address data is to be written or post decrementing said current location in said memory device after execution of said current instruction to generate said last location in said memory device where said address data was written to read said address data.  
 
     
     
         8 . A pre-decode pointer system with post revise operation in accordance with  claim 7  further comprising a slave latch circuit coupled to said master latch and to said increment decrement circuit for storing and sending to said master latch one of said next available location in said memory device to be written or said last location in said memory device where said address data was written.  
     
     
         9 . A pre-decode pointer system with post revise operation in accordance with  claim 7  wherein said selecting circuit is a multiplexer.  
     
     
         10 . A pre-decode stack pointer system with post revise operation comprising, in combination: 
 a stack memory device which stores and retrieves values of a program counter; and    a stack pointer coupled to said stack memory device for generating next unutilized location in said stack memory device to indicate where a current value of said program counter is to be written, for generating a directly preceding location to said next unutilized location to read a last value of said program counter written to said stack memory device, for selecting one of said next unutilized location in said stack memory device or said directly preceding location to said next unutilized location in said stack memory device, and for one of post incrementing or post decrementing said next unutilized location in said stack memory device after execution of a current instruction, wherein said stack pointer comprises: 
 a selection circuit coupled to said stack memory device for selecting and outputting said one of said next unutilized location in said stack memory device or said directly preceding location to said next unutilized address location in said stack memory device;  
 a master latch coupled to said selection circuit for storing said next unutilized location in said stack memory device;  
 an increment decrement circuit coupled to said selection circuit and to said master latch for pre-decrementing said next unutilized location in said stack memory device to generate said directly preceding location to said next unutilized location to read data from said last value of said program counter written to said stack memory device and for one of post incrementing said next unutilized location after execution of said current instruction to generate next available unutilized location in said stack memory device where a next value of said program counter is to be written or post decrementing said next unutilized location after execution of said current instruction to generate said directly preceding location to said unutilized location to read data from said last value of said program counter written to said stack memory device; and  
 a slave latch circuit coupled to said master latch and to said increment decrement circuit for storing and sending to said master latch one of said next available unutilized location in said stack memory device where a next value of said program counter is to be written or said directly preceding location to said unutilized location to read data from said last value of said program counter written to said stack memory device.  
   
     
     
         11 . A pre-decode pointer system with post revise operation in accordance with  claim 10  wherein said selection means is a multiplexer circuit.  
     
     
         12 . A method of providing a pre-decode stack pointer system with post revise operation comprising the steps of: 
 providing a stack memory device which stores and retrieves values of a program counter; and    providing a stack pointer coupled to said stack memory device for generating next unutilized location in said stack memory device to indicate where a current value of said program counter is to be written, for generating a directly preceding location to said next unutilized location to read a last value of said program counter written to said stack memory device, for selecting one of said next unutilized location in said stack memory device or said directly preceding location to said next unutilized location in said stack memory device, and for one of post incrementing or post decrementing said next unutilized location in said stack memory device after execution of a current instruction.    
     
     
         13 . The method of  claim 12  wherein said step of providing a stack pointer further comprises the steps of: 
 providing a selection circuit coupled to said stack memory device for selecting and outputting said one of said next unutilized location in said stack memory device or said directly preceding location to said next unutilized address location in said stack memory device;  
 providing a master latch coupled to said selection circuit for storing said next unutilized location in said stack memory device; and  
 providing an increment decrement circuit coupled to said selection circuit and to said master latch for pre-decrementing said next unutilized location in said stack memory device to generate said directly preceding location to said next unutilized location to read data from said last value of said program counter written to said stack memory device and for one of post incrementing said next unutilized location after execution of said current instruction to generate next available unutilized location in said stack memory device where a next value of said program counter is to be written or post decrementing said next unutilized location after execution of said current instruction to generate said directly preceding location to said unutilized location to read data from said last value of said program counter written to said stack memory device.  
 
     
     
         14 . The method of  claim 13  further comprising the step of providing a slave latch circuit coupled to said master latch and to said increment decrement circuit for storing and sending to said master latch one of said next available unutilized location in said stack memory device where a next value of said program counter is to be written or said directly preceding location to said unutilized location to read data from said last value of said program counter written to said stack memory device.  
     
     
         15 . The method of  claim 13  wherein said step of providing a selection circuit further comprises the step of providing a multiplexer circuit.