Structure of wires for a semiconductor device

Abstract

Disclosed are a method for forming a structure of wires for a semiconductor device in which pads are formed for contact in cell regions as well as core regions and periphery regions where cell aspect ratios are very high, and a structure of wires so formed. The semiconductor device includes a semiconductor substrate arranged into cell regions and periphery and/or core regions, the periphery and/or core regions having a well formed in the semiconductor substrate, the semiconductor substrate being arranged into active regions and field regions, the semiconductor device also having field insulating layers in the field regions, plural gate structures on portions of the semiconductor substrate in the active regions, and impurity regions in the semiconductor substrate between the gate structures. The method includes the steps of: forming an interlayer insulating structure on the semiconductor device; forming contact holes through the interlayer insulating structure to expose the impurity regions; lining contact-hole-portions of the interlayer insulating layer with portions of a barrier layer, respectively, such that the portions of the barrier layer contact the impurity regions; forming conductive pads on the portions of the barrier layer such that remainders of the contact holes are filled; and forming a wire layer on each one of the conductive pads.

What is claimed is:  
     
         1 . A structure of wires for a semiconductor device, the semiconductor device including a semiconductor substrate arranged into cell regions and at least one of a periphery region and a core region, the at least one of the periphery and core regions having a well formed thereunder, the semiconductor substrate being arranged into active regions and field regions, the semiconductor device also having field insulating layers in said field regions, a plurality of gate structures on portions of said semiconductor substrate in said active regions, and impurity regions in said semiconductor substrate between said gate structures, the structure of the wires comprising: 
 an interlayer insulating structure on said semiconductor device having contact holes through said interlayer insulating structure which expose said impurity regions;    portions of a titanium-compound barrier layer lining contact-hole-portions of said interlayer insulating layer, respectively, such that said portions of said barrier layer contact said impurity regions;    conductive pads on said portions of said barrier layer such that remainders of said contact holes are filled; and    a wire layer directly on each one of said conductive pads.    
     
     
         2 . The structure as claimed in  claim 1 , wherein said interlayer insulating structure includes: 
 a non-planarizing insulating layer on all exposed surfaces of gate structures and said semiconductor stusbrate; and    a planarizing insulating layer on said non-planarizing insulating layer.    
     
     
         3 . The structure as claimed in  claim 1 , wherein said conductive pads are formed of doped polysilicon.  
     
     
         4 . The structure as claimed in  claim 1 , wherein said semiconductor substrate is of a p-type conductivity, and said well is of n-type conductivity, and said conductive pads are at least one of said p-type and said n-type conductivity.  
     
     
         5 . The structure as claimed in  claim 1 , wherein said barrier layer is a silicide.  
     
     
         6 . The structure as claimed in  claim 1 , wherein said barrier layer is one of TiW, TiN, TiC, and TiB.