Semiconductor calibration structures, semiconductor calibration wafers, calibration methods of calibrating semiconductor wafer coating systems, semiconductor processing methods of ascertaining layer alignment during processing and calibration methods of calibrating multiple semiconductor wafer coating systems

Abstract

Semiconductor wafer coating system calibration structures and methods are described. In one embodiment, a calibration structure includes a perimetral edge bounding a calibration body. A calibration edge is spaced from the perimetral edge and is positioned over the calibration body. Together, the edges define a distance therebetween which is configured to calibrate a wafer coating system. In a preferred embodiment, the edges define respective termination distances configured to calibrate multiple different wafer coating systems. In another embodiment, a calibration pattern is formed over a semiconductor wafer. A layer of material is formed over the calibration pattern by a coating system, and selected portions thereof removed by the system. The positions of unremoved portions of the layer of material are inspected relative to the calibration pattern to ascertain whether the coating system removed the selected portions within desired tolerances. If not, the coating system is calibrated to within desired tolerances.

1 . A semiconductor wafer coating system calibration structure comprising: 
 a perimetral edge bounding a calibration body; and    a calibration edge spaced from said perimetral edge and positioned over said calibration body, said edges defining a distance therebetween configured to calibrate a wafer coating system.    
     
     
         2 . The calibration structure of  claim 1 , wherein said calibration edge defines, together with said perimetral edge, a plurality of different distances configured to calibrate said wafer coating system.  
     
     
         3 . The calibration structure of  claim 2 , wherein said calibration edge has a generally stepped appearance when viewed from over the calibration body.  
     
     
         4 . The calibration structure of  claim 1 , wherein said calibration edge comprises a plurality of spaced-apart, non-contiguous edges.  
     
     
         5 . The calibration structure of  claim 4 , wherein said spaced-apart, non-contiguous edges define, together with said perimetral edge, a plurality of different distances configured to calibrate said coating system.  
     
     
         6 . The calibration structure of  claim 1 , wherein said coating system comprises an edge bead removal unit.  
     
     
         7 . The calibration structure of  claim 6 , wherein said edge bead removal unit comprises a chemical edge bead removal unit.  
     
     
         8 . The calibration structure of  claim 6 , wherein said edge bead removal unit comprises an optical edge bead removal unit.  
     
     
         9 . The calibration structure of  claim 1 , wherein said distance is configured to calibrate multiple different coating systems.  
     
     
         10 . The calibration structure of  claim 9 , wherein said multiple different coating systems comprise edge bead removal units.  
     
     
         11 . A semiconductor wafer coating system calibration wafer comprising: 
 a perimetral edge bounding a wafer body; and    a layer of material disposed over the wafer body and having a calibration edge spaced inwardly of the said perimetral edge, said edges defining termination distances therebetween configured to calibrate multiple different wafer coating systems.    
     
     
         12 . The calibration wafer of  claim 11 , wherein said multiple different wafer coating systems comprise edge bead removal units.  
     
     
         13 . The calibration wafer of  claim 12 , wherein one of said edge bead removal units comprises a chemical edge bead removal unit.  
     
     
         14 . The calibration wafer of  claim 12 , wherein said one of said edge bead removal units comprises an optical edge bead removal unit.  
     
     
         15 . The calibration wafer of  claim 11 , wherein said calibration edge defines, together with said perimetral edge, a plurality of different distances configured to calibrate said multiple different wafer coating systems.  
     
     
         16 . The calibration wafer of  claim 15 , wherein said calibration edge has a generally stepped appearance when viewed from over the wafer.  
     
     
         17 . The calibration wafer of  claim 15 , wherein said calibration edge defines, in part, a generally contiguous calibration pattern.  
     
     
         18 . The calibration wafer of  claim 15 , wherein said calibration edge comprises a plurality of spaced-apart, non-contiguous edges.  
     
     
         19 . A semiconductor wafer coating system calibration wafer comprising: 
 a perimetral edge bounding a wafer body; and    a layer of material disposed over the wafer body and having a calibration edge spaced inwardly of the said perimetral edge, said edges defining a plurality of different termination distances therebetween configured to calibrate an edge bead removal unit.    
     
     
         20 . The calibration wafer of  claim 19 , wherein said calibration edge is contiguous.  
     
     
         21 . The calibration wafer of  claim 19 , wherein said calibration edge generally follows the shape of the perimetral edge.  
     
     
         22 . The calibration wafer of  claim 19 , wherein said calibration edge comprises a plurality of spaced-apart, non-contiguous edges.  
     
     
         23 . A calibration wafer for calibrating a plurality of wafer coating systems comprising: 
 a wafer having an outer edge having a shape which defines the wafer's periphery;    a calibration pattern distributed about a portion of said wafer proximate said periphery, said calibration pattern having first and second edges which generally follow at least a portion of said outer edge shape, and one joinder edge joined with one of the first and second edges and extending generally away from the outer edge.    
     
     
         24 . The calibration wafer of  claim 23 , wherein said calibration pattern comprises a first color, and said wafer comprises a second color intermediate said first and second edges and said wafer's outer edge, said first and second colors being different.  
     
     
         25 . The calibration wafer of  claim 23 , wherein said first and second edges are spaced inwardly of said wafer's outer edge different respective distances.  
     
     
         26 . The calibration wafer of  claim 23 , wherein said calibration pattern comprises a plurality of first and second edges, and a plurality of joinder edges joined with individual first and second edges.  
     
     
         27 . The calibration wafer of  claim 26 , wherein said plurality of first and second edges are spaced inwardly of said wafer's outer edge different respective distances.  
     
     
         28 . The calibration wafer of  claim 27 , wherein said plurality of first and second edges are disposed in an alternating fashion.  
     
     
         29 . The calibration wafer of  claim 27 , wherein said calibration pattern comprises a first color, and said wafer comprises a second color intermediate said plurality of said first and second edges and said wafer's outer edge, said first and second colors being different.  
     
     
         30 . A calibration method of calibrating a semiconductor wafer coating system comprising: 
 providing a semiconductor wafer having a calibration pattern;    using a coating system, forming a layer of material over the calibration pattern and removing selected portions of the layer of material; and    inspecting the position of unremoved portions of the layer of material relative to the calibration pattern to ascertain whether said coating system removed said selected portions within desired tolerances, and if not, calibrating said coating system.    
     
     
         31 . The calibration method of  claim 30 , wherein said wafer has an outer edge having a shape which defines the wafer's periphery, and: 
 the calibration pattern comprises first and second calibration edges which generally follow at least a portion of said outer edge shape,    said removing of said selected portions of said layer of material defines a material edge, and    said inspecting comprises determining whether said material edge is disposed in a desired position relative to said first and second edges.    
     
     
         32 . The calibration method of  claim 31 , wherein said first and second calibration edges are disposed at different respective distances relative to said wafer's outer edge.  
     
     
         33 . The calibration method of  claim 32 , wherein said inspecting comprises ascertaining whether said material edge is disposed intermediate said first and second edges when viewed from over the wafer.  
     
     
         34 . The calibration method of  claim 31 , wherein: 
 said first and second calibration edges comprise a plurality of first and second calibration edges at different respective distances relative to said wafer's outer edge, said edges being disposed in an alternating fashion about the wafer's periphery; and    said inspecting comprises ascertaining whether said material edge is disposed intermediate the first and second edges when viewed from over the wafer.    
     
     
         35 . A semiconductor processing method of ascertaining layer alignment during processing comprising: 
 forming a layer of material over a calibration substrate, said calibration substrate having a perimetral edge bounding an interior calibration body;    patterning and etching said layer of material to define a plurality of calibration edges positioned over said calibration body and spaced different selected distances from said perimetral edge, said distances being configured to calibrate a semiconductor wafer coating system;    using a semiconductor wafer coating system, forming a different layer of material over the calibration substrate and removing said different layer sufficient to remove selected portions of the different layer from over the substrate; and    inspecting the position of unremoved portions of the different layer of material relative to one of the selected distances to ascertain whether said coating system removed said selected portions within desired tolerances.    
     
     
         36 . The calibration method of  claim 35 , wherein said removing of said different layer of material defines a material edge, and said inspecting comprises ascertaining whether said material edge is disposed between two of said calibration edges when viewed from over said substrate.  
     
     
         37 . The calibration method of  claim 35 , wherein said calibration substrate's perimetral edge has a shape which defines the substrate's periphery, and: 
 said patterning and etching comprises forming said calibration edges to generally follow at least a portion of said perimetral edge shape,    said removing of said different layer of material defines a material edge, and    said inspecting comprises ascertaining whether said material edge is disposed in a desired position relative to said calibration edges when viewed from over said substrate.    
     
     
         38 . The calibration method of  claim 37 , wherein said inspecting comprises ascertaining whether said material edge is disposed intermediate said first and second edges when viewed from over said substrate.  
     
     
         39 . The calibration method of  claim 37 , wherein the etching of said layer of material to define said plurality of calibration edges comprising forming said edges to alternate thereby defining different first and second distances relative to said perimetral edge.  
     
     
         40 . A calibration method of calibrating multiple semiconductor wafer coating systems comprising: 
 forming a calibration pattern over a semiconductor wafer;    using a first wafer coating system, forming a first patterned masking layer over the calibration pattern;    inspecting the position of the first patterned masking layer relative to the calibration pattern to ascertain whether said first coating system formed said first patterned masking layer over the calibration pattern within desired tolerances, and if not, calibrating said first coating system;    removing the first patterned masking layer;    using a second wafer coating system, forming a second patterned masking layer over the calibration pattern; and    inspecting the position of the second patterned masking layer relative to the calibration pattern to ascertain whether said second coating system formed said second patterned masking layer over the calibration pattern within desired tolerances, and if not, calibrating said second coating system.    
     
     
         41 . The calibration method of claim  40 , wherein said semiconductor wafer has an outer edge having a shape which defines the wafer's periphery, and said forming of said calibration pattern comprises forming first and second calibration edges which generally follow at least a portion of the outer edge shape.  
     
     
         42 . The calibration method of claim  41 , wherein said first and second calibration edges are spaced inwardly of said outer edge different respective distances.  
     
     
         43 . The calibration method of claim  42 , wherein said forming of said first and second patterned masking layers comprises forming respective masking layer edges, and said inspecting steps comprise ascertaining whether said respective masking layer edges are disposed intermediate said first and second calibration edges when viewed from over the substrate.