Formulation of multiple gate oxides thicknesses without exposing gate oxide or silicon surface to photoresist

Abstract

A method and structure for forming an integrated circuit chip having multiple-thickness gate dielectrics includes forming a gate dielectric layer over a substrate, forming a sacrificial layer over the gate dielectric layer, forming first openings through the sacrificial layer to expose the gate dielectric layer in the first openings, growing a first gate dielectric having a thickness greater than that of the gate dielectric layer in the first openings, depositing a first gate conductor above the first gate dielectric in the first openings, forming a second opening through the sacrificial layer to expose the gate dielectric layer in the second opening, and depositing a second gate conductor in the second opening.

What is claimed is:  
     
         1 . A method of forming and integrated circuit chip having multiple-thickness gate dielectrics, said method comprising: 
 forming a gate dielectric layer over a substrate;    forming a sacrificial layer over said gate dielectric layer;    forming first openings through said sacrificial layer to expose said gate dielectric layer in said first openings;    growing a first gate dielectric having a thickness greater than that of said gate dielectric layer in said first openings;    depositing a first gate conductor above said first gate dielectric in said first openings;    forming a second opening through said sacrificial layer to expose said gate dielectric layer in said second opening; and    depositing a second gate conductor in said second opening.    
     
     
         2 . The method in  claim 1 , further comprising forming shallow trench isolation regions within said substrate, wherein, said first opening and said second opening are formed between said shallow trench isolation regions.  
     
     
         3 . The method in  claim 1 , wherein said forming of said sacrificial layer comprises forming a first sacrificial layer and forming a second sacrificial layer over said first sacrificial layer.  
     
     
         4 . The method in  claim 3 , wherein said first sacrificial layer comprises a material that is selectively etchable with respect to said gate dielectric layer.  
     
     
         5 . The method in  claim 4 , further comprising, after said depositing of said second gate conductor, removing said first sacrificial layer such that said second sacrificial layer is simultaneously removed.  
     
     
         6 . The method in  claim 1 , further comprising after said depositing of said first gate conductor, planarizing said sacrificial layer.  
     
     
         7 . The method in  claim 1 , wherein said first gate conductor has a thickness less than that of said second gate conductor.  
     
     
         8 . A method of forming an integrated circuit chip having multiple-thickness gate dielectrics, said method comprising: 
 forming gate mandrels on a substrate;    forming an insulator between said gate mandrels;    selectively removing first ones of said gate mandrels to form first openings in said insulator;    forming a first gate dielectric within said first openings;    depositing a first gate conductor within said first openings and above said first gate dielectric;    selectively removing second ones of said gate mandrels to form second openings in said insulator;    forming a second gate dielectric within said second openings, said second gate dielectric having a thicknesses less than that of said first gate dielectric; and    depositing a second gate conductor within said second openings above said second gate dielectric.    
     
     
         9 . The method in  claim 8 , further comprising, before said forming of said insulator, forming source and drain regions adjacent said gate mandrels.  
     
     
         10 . The method in  claim 9 , further comprising, before said forming of said source and drain regions, forming insulating spacers on said gate mandrels.  
     
     
         11 . The method in  claim 8 , further comprising, before said removing of said first ones of said mandrels, patterning a mask over said mandrels and said insulators.  
     
     
         12 . The method in  claim 8 , wherein said first gate dielectric and said second gate dielectric comprise different materials.  
     
     
         13 . The method in  claim 8 , wherein said forming of said mandrels comprises depositing a gate mandrel material and patterning said gate mandrel material to remain only where gate conductor stacks are to be positioned.  
     
     
         14 . The method in  claim 8 , further comprising, before said forming of said gate mandrels, forming a pad layer over said substrate, such that said pad layer is positioned between said gate mandrels and said substrate, wherein said first opening and said second opening extend through said pad layer.  
     
     
         15 . An integrated circuit chip comprising: 
 first devices having a first gate dielectric with a first gate dielectric thickness; and    second devices having a second gate dielectric with a second gate dielectric thickness less than said first gate dielectric thickness,    wherein said first gate dielectric and said second gate dielectric are free of photoresist impurities.    
     
     
         16 . The integrated circuit chip in  claim 15 , wherein said photoresist impurities include sodium, potassium, iron and nickel.  
     
     
         17 . The integrated circuit chip in  claim 15 , further comprising: 
 a first gate conductor over said first gate dielectric, said first gate conductor having a first gate conductor thickness; and    a second gate conductor over said second gate dielectric, said second gate conductor having a second gate conductor thickness greater than said first gate conductor thickness.    
     
     
         18 . The integrated circuit chip in  claim 17 , further comprising insulating spacers adjacent said first gate conductor, said first gate dielectric, and said second gate conductor.  
     
     
         19 . The integrated circuit chip in  claim 17 , further comprising source and drain regions adjacent said first gate conductor and said second gate conductor.  
     
     
         20 . The integrated circuit chip in  claim 15 , wherein said first gate dielectric and said second gate dielectric comprised different materials.