Variable delay circuit

Abstract

A variable delay circuit comprising a positive logic variable delay circuit for delaying an edge of a signal input through an input terminal and a negative logic variable delay circuit for delaying an edge of a signal input through an input terminal, in which only an edge delayed in accordance with the set time is extracted from all the edges of a signal supplied from the positive logic variable delay circuit and all the edges of a signal supplied from the negative logic variable delay circuit.

What is claimed is:  
     
         1 . A variable delay circuit comprising: 
 an input terminal;    a positive logic variable delay circuit for delaying an edge of a signal input through said input terminal;    a negative logic variable delay circuit for delaying an edge of a signal input through said input terminal; and    an extracting circuit for extracting only the edge delayed in accordance with set time from the edges of a signal supplied from said positive logic variable delay circuit and the edges of a signal supplied from said negative logic variable delay circuit.    
     
     
         2 . A variable delay circuit as set forth in  claim 1 , wherein 
 said positive logic variable delay circuit includes delay time increasing means for making more than the set time, the delay time of an edge, varying from a low to high level, of a signal input through said input terminal, while    said negative logic variable delay circuit includes delay time decreasing means for making less than the set time, the delay time of an edge, varying from a high to low level, of a signal input through said input terminal.    
     
     
         3 . A variable delay circuit as set forth in  claim 1 , wherein said extracting circuit is an OR circuit which computes OR of a signal supplied from said positive logic variable delay circuit and a signal supplied from said negative logic variable delay circuit.  
     
     
         4 . A variable delay circuit as set forth in  claim 1 , wherein said positive logic variable delay circuit includes delay time increasing means for making more than the set time, the delay time of an edge, varying from a low to high level, of a signal input through said inputs terminal, while said negative logic variable delay circuit includes delay time decreasing means for making less than the set time, the delay time of an edge, varying from a high to low level, of a signal input through said input terminal and said extracting circuit is an OR circuit which computes OR of a signal supplied from said positive logic variable delay circuit and a signal supplied from said negative logic variable delay circuit.  
     
     
         5 . A variable delay circuit as set forth in  claim 1 , wherein said positive logic variable delay circuit includes delay time increasing means for making more than the set time, the delay time of an edge, varying from a low to high level, of a signal input through said input terminal, while 
 said negative logic variable delay circuit includes delay time decreasing means for making less than the set time, the delay time of an edge, varying from a high to low level, of a signal input through said input terminal,    said delay time increasing means and said delay time decreasing means respectively including a capacitive element and adjusting the delay time by setting the capacity of the capacitive element.    
     
     
         6 . A variable delay circuit as set forth in  claim 1 , wherein said positive logic variable delay circuit includes a first delay circuit for delaying an edge, varying from a high to low level, of a signal input through said input terminal and supplying the logic being inverted, and 
 a second delay circuit for delaying an edge, varying from a high to low level, of a signal supplied from said first delay circuit and supplying the logic being inverted, while    said negative logic variable delay circuit includes a first inverter for inverting the logic of a signal input through said input terminal, a third delay circuit for delaying an edge, varying from a high to low level, of a signal supplied from said first inverter and supplying the logic being inverted,    a fourth delay circuit for delaying an edge, varying from a high to low level, of a signal supplied from said third delay circuit and supplying the logic being inverted, and    a second inverter for inverting the logic of a signal supplied from said fourth delay circuit.    
     
     
         7 . A variable delay circuit as set forth in  claim 6 , wherein said positive logic variable delay circuit includes a buffer whose operating speed is equal to the addition of the operating speed of said first inverter and that of said second inverter.  
     
     
         8 . A variable delay circuit as set forth in  claim 1 , wherein said positive logic variable delay circuit includes delay time increasing means for making more than the set time, the delay time of an edge, varying from a low to high level, of a signal input through said input terminal, 
 a first delay circuit for delaying an edge, varying from a high to low level, of a signal input through said input terminal and supplying the logic being inverted, and    a second delay circuit for delaying an edge, varying from a high to low level, of a signal supplied from said first delay circuit and supplying the logic being inverted, while    said negative logic variable delay circuit includes delay time decreasing means for making less than the set time, the delay time of an edge, varying from a high to low level, of a signal input through said input terminal,    a first inverter for inverting the logic of a signal input through said input terminal,    a third delay circuit for delaying an edge, varying from a high to low level, of a signal supplied from said first inverter and supplying the logic being inverted,    a fourth delay circuit for delaying an edge, varying from a high to low level, of a signal supplied from said third delay circuit and supplying the logic being inverted, and    a second inverter for inverting the logic of a signal supplied from said fourth delay circuit.    
     
     
         9 . A variable delay circuit as set forth in  claim 8 , wherein 
 said delay time increasing means and said delay time decreasing means respectively including a capacitive element and adjusting the delay time by setting the capacity of the capacitive element.    
     
     
         10 . A variable delay circuit as set forth in  claim 1 , wherein said positive logic variable delay circuit includes 
 a first delay circuit for delaying an edge, varying from a high to low level, of a signal input through said input terminal and supplying the logic being inverted, and    a second delay circuit for delaying an edge, varying from a high to low level, of a signal supplied from said first delay circuit and supplying the logic being inverted, while    said negative logic variable delay circuit includes    a first inverter for inverting the logic of a signal input through said input terminal,    a third delay circuit for delaying an edge, varying from a high to low level, of a signal supplied from said first inverter and supplying the logic being inverted,    a fourth delay circuit for delaying an edge, varying from a high to low level, of a signal supplied from said third delay circuit and supplying the logic being inverted, and    a second inverter for inverting the logic of a signal supplied from said fourth delay circuit, said first delay circuit having a first capacitive element which is charged upon receipt of an edge varying from a low to high level and discharged upon receipt of an edge varying from a high to low level,    said second delay circuit having a second capacitive element which is charged upon receipt of an edge varying from a low to high level and discharged upon receipt of an edge varying from a high to low level,    said third delay circuit having a third capacitive element which is charged upon receipt of an edge varying from a low to high level and discharged upon receipt of an edge varying from a high to low level,    said fourth delay circuit having a fourth capacitive element which is charged upon receipt of an edge varying from a low to high level and discharged upon receipt of an edge varying from a high to low level.    
     
     
         11 . A variable delay circuit as set forth in  claim 10 , wherein the capacity of said first capacitive element is equal to that of said third capacitive element, the capacity of said second capacitive element is greater than that of said first capacitive element and said third capacitive element, and the capacity of said fourth capacitive element is smaller than that of said first capacitive element and said third capacitive element.  
     
     
         12 . A variable delay circuit as set forth in  claim 1 , wherein said positive logic variable delay circuit includes a first delay circuit for delaying an edge, varying from a high to low level, of a signal input through said input terminal and supplying the logic being inverted, and 
 a second delay circuit for delaying an edge, varying from a high to low level, of a signal supplied from said first delay circuit and supplying the logic being inverted, while    said negative logic variable delay circuit includes a first inverter for inverting the logic of a signal input through said input terminal, a third delay circuit for delaying an edge,    varying from a high to low level, of a signal supplied from said first inverter and supplying the logic being inverted,    a fourth delay circuit for delaying an edge, varying from a high to low level, of a signal supplied from said third delay circuit and supplying the logic being inverted, and    a second inverter for inverting the logic of a signal supplied from said fourth delay circuit, said first delay circuit having a first capacitive element which is charged upon receipt of an edge varying from a low to high level and a first constant-current power for discharging said first capacitive element upon receipt of an edge varying from a high to low level,    said second delay circuit having a second capacitive element which is charged upon receipt of an edge varying from a low to high level and a second constant-current power for discharging said second capacitive element upon receipt of an edge varying from a high to low level,    said third delay circuit having a third capacitive element which is charged upon receipt of an edge varying from a low to high level and a third constant-current power for discharging said third capacitive element upon receipt of an edge varying from a high to low level,    said fourth delay circuit having a fourth capacitive element which is charged upon receipt of an edge varying from a low to high level and a fourth constant-current power for discharging said fourth capacitive element upon receipt of an edge varying from a high to low level.    
     
     
         13 . A variable delay circuit as set forth in  claim 12 , wherein the capacity of said first capacitive element is equal to that of said fourth capacitive element, the current of said first constant-current power is equal to that of said third constant-current power, the current of said second constant-current power is smaller than that of said first constant-current power and said third constant-current power, and the current of said fourth constant-current power is greater than that of said first constant-current power and said third constantcurrent power.  
     
     
         14 . A variable delay circuit as set forth in  claim 1 , wherein said extracting circuit consists of a first fixed delay circuit for generating a constant delay on a signal supplied from said positive logic variable delay circuit, 
 an OR circuit for calculating OR of a signal supplied from said first fixed delay circuit and a signal supplied from said negative logic variable delay circuit,    a second fixed delay circuit for generating the constant delay on a signal supplied from said OR circuit, and    an AND circuit for calculating AND of a signal supplied from said second fixed delay circuit and a signal supplied from said OR circuit.    
     
     
         15 . A variable delay circuit as set forth in  claim 1 , wherein said positive logic variable delay circuit includes delay time increasing means for making more than the set time, the delay time of an edge, varying from a low to high level, of a signal input through said input terminal, while 
 said negative logic variable delay circuit includes delay time decreasing means for making less than the set time, the delay time of an edge, varying from a high to low level, of a signal input through said input terminal, and    said extracting circuit consists of a first fixed delay circuit for generating a constant delay on a signal supplied from said positive logic variable delay circuit,    an OR circuit for calculating OR of a signal supplied from said first fixed delay circuit and a signal supplied from said negative logic variable delay circuit,    a second fixed delay circuit for generating the constant delay on a signal supplied from said OR circuit, and an AND circuit for calculating AND of a signal supplied from said second fixed delay circuit and a signal supplied from said OR circuit.