Bit line structure for semiconductor device

Abstract

A bit line structure for semiconductor devices, and a fabrication method thereof are provided. In this method, a first conductive layer pattern, which fills a first contact hole and is used as a bit line, is formed on a first dielectric layer pattern having the first contact hole formed on a semiconductor substrate. A lower part protecting layer pattern, comprised of an anti-reflectance coating (ARC) layer used in a process for patterning the first dielectric layer pattern, is formed on the interface between the first conductive layer pattern and the first dielectric layer pattern. A spacer for covering the sidewall of the first conductive layer pattern is formed. An upper part protecting layer pattern comprised of an upper ARC layer is formed to cover the upper part of the first conductive layer pattern. A second dielectric layer pattern having a second contact hole is formed to cover the first conductive layer pattern. A second conductive layer pattern filling the second contact hole is formed and used as a storage node of a capacitor.

What is claimed is:  
     
         1 . A bit line structure for semiconductor devices, comprising: 
 a first dielectric layer pattern formed on a semiconductor substrate, the first dielectric layer pattern having a first contact hole exposing a part of the semiconductor substrate;    a first conductive layer pattern formed on the first dielectric layer pattern, filling the first contact hole, and used as a bit line;    a lower protecting layer pattern which protects a lower surface of the first conductive layer pattern on an interface between the first conductive layer pattern and the first dielectric layer pattern, the lower protecting layer pattern comprising an anti-reflectance coating (ARC) layer;    a spacer on a sidewall of the first conductive layer pattern;    an upper protecting layer pattern which covers and protects an upper surface of the first conductive layer pattern, the upper protecting layer pattern comprising an ARC layer; and    a second dielectric layer pattern which insulates the first conductive layer pattern, is isolated from the first conductive layer pattern, and has a second contact hole for exposing the semiconductor substrate.    
     
     
         2 . The bit line structure for semiconductor devices as claimed in  claim 1 , wherein the spacer is formed of a nitride material selected from the group consisting of silicon nitride and silicon oxynitride.  
     
     
         3 . The bit line structure for semiconductor devices as claimed in  claim 1 , wherein the lower protecting layer pattern is a nitride-based ARC layer.  
     
     
         4 . The bit line structure for semiconductor devices as claimed in  claim 1 , wherein the upper protecting layer pattern is a nitride-based ARC layer.  
     
     
         5 . The bit line structure for semiconductor devices as claimed in  claim 1 , further comprising: 
 a second conductive layer pattern formed on the second dielectric layer pattern, for filling the second contact hole.    
     
     
         6 . The bit line structure for semiconductor devices as claimed in  claim 1 , wherein the lower protecting layer pattern does not cover a sidewall of the first contact hole.