Method for manufacturing buried layer with low sheet resistence and structure formed thereby

Abstract

The present invention provide a method for reducing the sheet resistance of the buried layer serving as the bit line or an interconnect of a semiconductor device. The method includes steps of providing the silicon substrate, doping the silicon substrate for forming an extrinsic silicon region, and forming a silicide layer on the extrinsic silicon region for obtaining a low-resistance buried layer.

What is claimed is:  
     
         1 . A method for forming a low-resistance buried layer on a silicon substrate of a semiconductor device, comprising steps of: 
 providing said silicon substrate;    doping said silicon substrate for forming an extrinsic silicon region; and    forming a silicide layer on said extrinsic silicon region for obtaining said low-resistance buried layer.    
     
     
         2 . A method according to  claim 1  wherein said semiconductor device includes a memory array, and said low-resistance buried layer is a bit line of said memory array.  
     
     
         3 . A method according to  claim 1  wherein said low-resistance buried layer is an interconnect of said semiconductor device.  
     
     
         4 . A method according to  claim 1  wherein said step for doping said silicon substrate includes steps of: 
 forming a silicon nitride layer over said silicon substrate;  
 etching said silicon nitride layer to expose a portion of said silicon substrate for forming said buried layer; and  
 doping said portion of said silicon substrate to obtain said extrinsic silicon region.  
 
     
     
         5 . A method according to  claim 4  wherein said step for forming said silicide layer on said extrinsic silicon region includes steps of: 
 forming a spacer on a sidewall of said silicon nitride layer; and  
 executing a salicide process by using said silicon nitride layer and said spacer as a mask to obtain said silicide layer.  
 
     
     
         6 . A method according to  claim 5  wherein said step for forming said spacer on said sidewall of said silicon nitride layer includes steps of: 
 forming an dielectric layer over said silicon nitride layer; and  
 executing a spacer etching for obtaining said spacers.  
 
     
     
         7 . A method according to  claim 6  wherein said dielectric layer is a silicon dioxide layer, and said silicon dioxide layer is made from tetra-ethyl-ortho-silicate (TEOS).  
     
     
         8 . A method according to  claim 5  wherein said salicide process includes steps of: 
 depositing a titanium/titanium nitride (Ti/TiN) layer on said silicon substrate;  
 executing a first rapid thermal processing to form a titanium silicide (TiSi x ) layer on the junction of said silicon substrate and said titanium/titanium nitride layer; and  
 executing a selective etching for removing said titanium/titanium nitride layer and remaining said titanium silicide layer on said silicon substrate.  
 
     
     
         9 . A method according to  claim 8  wherein said first rapid thermal processing is executed at a temperature of about 650° C. and under a nitride atmosphere.  
     
     
         10 . A method according to  claim 8  wherein said step salicide process further includes steps of: 
 executing a second rapid thermal processing for reducing the resistance of said titanium silicide layer.  
 
     
     
         12 . A method according to claim  11  wherein said second rapid thermal processing is executed at a temperature of about 825° C. and under a nitride atmosphere.  
     
     
         13 . A method according to  claim 1 , further comprising a step of: 
 forming an oxide layer over said silicide layer.    
     
     
         14 . A method according to claim  13 , further comprising a step of: 
 forming a polysilicon layer above said oxide layer and said silicide layer, wherein said silicide layer is protected by said oxide layer during forming said polysilicon layer.    
     
     
         15 . A method according to claim  14 , further comprising a step of forming a spacer on a sidewall of said silicide layer beforing forming said polysilicon layer, wherein said sidewall of said silicide layer is protected by said spacer during forming said polysilicon layer.  
     
     
         16 . A method according to claim  13 , further comprising a step of: executing a planarization process on said oxide layer.  
     
     
         17 . A low-resistance buried layer structure according to  claim 1 , comprising: 
 said silicon substrate;    said extrinsic silicon region formed by doping a dopant into a portion of said silicon substrate wherein said portion of said silicon substrate is used for forming said buried layer; and    said silicide layer formed on a surface of said extrinsic silicon region.    
     
     
         18 . A low-resistance buried layer structure according to claim  17  wherein said buried layer structure is one of a bit line and an interconnect of said semiconductor device.  
     
     
         19 . A low-resistance buried layer structure according to claim  17  wherein said silicide layer is a titanium silicide (TiSi x ) layer.  
     
     
         20 . A low-resistance buried layer structure according to claim  19  wherein said titanium silicide layer is formed by a first rapid thermal processing to have a C49 phase, and then processed by a second rapid thermal processing to have a C54 phase.  
     
     
         21 . A low-resistance buried layer structure according to claim  17  wherein said dopant is one of phosphorus and arsenic.  
     
     
         22 . A low-resistance buried layer structure according to claim  17 , further comprising an oxide layer covering said silicide layer.  
     
     
         23 . A low-resistance buried layer structure according to  claim 22 , further comprising a spacer covering a sidewall of said silicide layer.  
     
     
         24 . A low-resistance buried layer structure according to  claim 23 , further comprising a polysilicon layer covering said oxide layer and said spacer, wherein said silicide layer is protected by said oxide layer and said spacer during forming said polysilicon layer.