Reducing lithography limitation by reverse-offset spacer process

Abstract

A method for forming semiconductor devices is disclosed. The method of the present invention includes providing a semiconductor substrate, followed by forming shallow trench isolation (STI) process, and then a dummy gate is formed by silicon nitride layer which is deposited and defined. With appropriate wet etching, this dummy poly can be removed. After local punch-through implantation, reverse offset spacer is formed to reduce Cgd (capacitance is between gate and drain) and poly-CD (critical dimension). Polysilicon is deposited followed by polysilicon CMP. After thick Ti-salicidation, the usual CMOS (Complementary Metal-Oxide-Semiconductor) processes are proceeded.

What is claimed is:  
     
         1 . A method for forming a semiconductor device, comprising: 
 providing a semiconductor substrate;    forming a first oxide layer on said substrate;    forming a dummy gate on said substrate;    ion firstly implanting said semiconductor substrate using said dummy gate as a first mask to form a lightly doped drain region in said semiconductor substrate;    forming a first spacer on said sidewall of said dummy gate;    ion secondly implanting said semiconductor substrate using said dummy gate and said first spacer as a second mask to form a source/drain region in said semiconductor substrate;    forming a first silicide layer on said source/drain region;    forming a dielectric layer over said semiconductor substrate, and a top surface of said dummy gate is exposed;    forming a trench by means of removing said dummy gate;    forming an antipunch-through region under said trench of said semiconductor substrate;    forming a second spacer in inner sidewall of said trench;    removing said first oxide layer in said trench;    forming a second oxide layer in said trench;    forming a gate by means of depositing a conductive layer in said trench; and    forming a second silicide layer on said gate.    
     
     
         2 . The method according to  claim 1 , wherein said semiconductor substrate further comprises to formed a shallow trench isolation region formed under said semiconductor substrate.  
     
     
         3 . The method according to  claim 1 , wherein the method for forming said dummy gate comprises: 
 depositing a first silicon nitride layer on the semiconductor substrate; and    defining and etching said first silicon nitride layer to take advantage of photolithography process for the purpose of forming said dummy gate.    
     
     
         4 . The method according to  claim 3 , wherein said first silicon nitride layer is formed on said semiconductor substrate by means of chemical vapor deposition.  
     
     
         5 . The method according to  claim 1 , wherein the method for forming said first spacer comprises: 
 depositing a first silicon dioxide layer on said semiconductor substrate; and    etching said first silicon dioxide layer to take advantage of anisotropic etching, so as to form said first spacer on sidewall of said dummy gate.    
     
     
         6 . The method according to  claim 1 , wherein said first silicide layer is formed on said source/drain region by means of salicidation.  
     
     
         7 . The method according to  claim 1 , wherein the method for forming said dielectric layer comprises: 
 forming a second silicon dioxide layer over said semiconductor substrate; and    polishing said second silicon dioxide layer by means of chemical mechanical polishing stop to expose top surface of said dummy gate.    
     
     
         8 . The method according to  claim 1 , wherein said dummy gate is removed by wet etching, and so as to form said trench.  
     
     
         9 . The method according to  claim 1 , wherein said wet etching uses phosphoric solution.  
     
     
         10 . The method according to  claim 1 , wherein said antipunch-through region is formed by local punch-through implantation in said trench.  
     
     
         11 . The method according to  claim 1 , wherein the method for forming said second spacer comprises: 
 depositing a second silicon nitride layer on the semiconductor substrate, by means of chemical vapor deposition; and    etching said second silicon nitride layer be means of anisotropically etching for the purpose of forming said second spacer on inner sidewall surface of said trench.    
     
     
         12 . The method according to  claim 1 , wherein said second oxide layer has a thickness that is about 20 angstroms and 30 angstroms.  
     
     
         13 . The method according to  claim 1 , wherein the method for forming said second spacer comprises: 
 depositing and filling said trench of said semiconductor substrate with a polysilicon layer, so as to be conductive layer; and    polishing said polysilicon layer stop to expose surface of said dielectric layer so as to form said gate.    
     
     
         14 . The method according to  claim 13 , wherein said polish of said conductive layer is chemical mechanical polishing.  
     
     
         15 . The method according to  claim 1 , wherein said second silicide is formed on said gate by salicidation.  
     
     
         16 . A method for forming a semiconductor device, comprising: 
 providing a semiconductor substrate having at least a dielectric layer is formed therein, and said dielectric layer have at least a trench;    forming a spacer on inner sidewall of said trench;    depositing a conductive layer in said trench, so as to form a gate; and    forming a first silicide layer on said gate.    
     
     
         17 . The method according to  claim 16 , further comprises: 
 forming a shallow trench isolation region in said semiconductor substrate;    forming a gate oxide layer on said trench of said semiconductor substrate and site under said dielectric layer;    forming a source/drain region under opposite side of trench of semiconductor substrate; and    forming a second silicide layer on said source/drain region.    
     
     
         18 . The method according to  claim 16 , wherein the method for forming said spacer comprises: 
 depositing a silicon nitride layer on the semiconductor substrate and surface of said trench, by means of chemical vapor deposition; and    etching said silicon nitride layer to take advantage of anisotropic etching for the purpose of forming said spacer on inner sidewall surface of said trench.    
     
     
         19 . The method according to  claim 16 , wherein the method for forming said gate comprises: 
 depositing and fill said trench of said semiconductor substrate with a polysilicon layer, so as to be said conductive layer; and    polishing said polysilicon layer stop to expose surface of said dielectric layer, so as to form said gate.    
     
     
         20 . The method according to  claim 16 , wherein said first silicide is formed on said gate, so as to salicidation.