Low leakage capacitance isolation material

Abstract

A method for reducing a capacitance formed on a silicon substrate. The capacitance has, as a dielectric material thereof, a silicon dioxide layer on a surface of the silicon substrate. The method includes the step of introducing hydrogen atoms into a portion of said surface to increase the dielectric constant of such portion of the surface increasing the effective thickness of the dielectric material and hence reducing said capacitance. The method including the step of forming the silicon dioxide layer with a thickness greater than two nanometers. The step of introducing hydrogen comprises the step of forming hydrogen atoms in the surface with concentrations of 10 17 atoms per cubic centimeter, or greater. In one embodiment the hydrogen atoms are formed by baking in hydrogen at a temperature of 950° C. to 1100° C. and pressure greater than 100 Torr. A trench capacitor DRAM cell is provided wherein the hydrogen provides a passivation layer to increase the effective capacitance around a collar region and thereby reduce unwanted transistor action.

1 . A method for forming a dielectric material on silicon material, comprising the step of: 
 forming a dielectric layer of silicon dioxide on the surface of the silicon; and    reducing a dielectric constant between the silicon dioxide and the silicon comprising the step of treating said surface with hydrogen.    
     
     
         2 . The method recited in  claim 1  wherein the silicon dioxide forming step comprises the step of forming such silicon dioxide with a thickness greater than two nanometers.  
     
     
         3 . The method recited in  claim 2  the step of treating said surface with hydrogen comprises the step of baking in a hydrogen at a temperature of 950° C. to 1100° C. and pressure greater than 100 Torr.  
     
     
         4 . The method recited in  claim 2  wherein the step of treating said surface with hydrogen comprises the step of forming hydrogen atoms in the surface with concentrations of at least 10 17  atoms per cubic centimeter, or greater.  
     
     
         5 . The method recited in  claim 2  wherein the step of treating said surface with hydrogen comprises the step of implanting hydrogen atoms into the surface with concentrations of at least 10 17  atoms per cubic centimeter, or greater.  
     
     
         6 . A method for forming a dielectric on silicon, comprising the step of: 
 forming a layer of silicon dioxide on the surface of the silicon with a thickness greater than two nanometers; and    treating said surface with hydrogen.    
     
     
         7 . The method recited in  claim 6  wherein the step of treating said surface with hydrogen comprises the step of baking in a hydrogen at a temperature of 950° C. to 1100° C. and pressure greater than 100 Torr.  
     
     
         8 . A method for forming a dielectric on silicon, comprising the step of: 
 forming a layer of silicon dioxide on the surface of the silicon; and    reducing the dielectric constant between the silicon dioxide and the silicon by a factor of at least ten comprising the step of treating said surface with hydrogen.    
     
     
         9 . The method recited in  claim 8  wherein the silicon dioxide forming step comprises the step of forming such silicon dioxide with a thickness greater than two nanometers.  
     
     
         10 . The method recited in  claim 9  the step of treating said surface with hydrogen comprises the step of baking in a hydrogen at a temperature of 950° C. to 1100° C. and pressure greater than 100 Torr.  
     
     
         11 . The method recited in  claim 9  wherein the step of treating said surface with hydrogen comprises the step of forming hydrogen atoms in the surface with concentrations of atoms 10 17  atoms per cubic centimeter, or greater.  
     
     
         12 . A method for forming reducing a capacitance formed on a silicon substrate, such capacitance having, as a dielectric material thereof, a silicon dioxide layer on a surface of the silicon substrate, comprising the step of: 
 introducing hydrogen atoms into a portion of said surface to increase the dielectric constant of such portion of the surface increasing the effective thickness of the dielectric material and hence reducing said capacitance.    
     
     
         13 . The method recited in  claim 12  including the step of forming the silicon dioxide layer with a thickness greater than two nanometers.  
     
     
         14 . The method recited in  claim 13  the step of introducing hydrogen comprises baking in a hydrogen at a temperature of 950° C. to 1100° C. and pressure greater than 100 Torr.  
     
     
         15 . The method recited in  claim 13  wherein the step of introducing hydrogen comprises the step of forming hydrogen atoms in the surface with concentrations of 10 17  atoms per cubic centimeter, or greater.  
     
     
         16 . A DRAM cell having a transistor coupled to a capacitor, comprising: 
 a silicon substrate having: 
 (a) the transistor, such transistor having source and drain regions having a first type conductivity disposed in an upper portion of the substrate, such source and drain regions being disposed in a well in the substrate, such well having a conductivity type opposite to the first type conductivity; and,  
 (b) the capacitor, comprising: 
 (i) a trench disposed in the substrate;  
 (ii) a first dielectric layer disposed on intermediate and lower walls of the trench;  
 (iii) a first conductive material disposed in the trench on the first dielectric layer and an upper portion of such first conductive material being electrically connected to one of the source and drain regions through a node region disposed in the substrate between such one of the source and drain regions and the upper portion of the first conductive material in the trench, such first conductive material providing a first electrode for the capacitor; and  
 (iv) a second conductive material disposed in the substrate about the lower portion of the trench, such second conductive material having the first type conductivity, such second conductive material being dielectrically separated from the first conductive material by the lower portion of the first dielectric material, such second conductive material providing a second electrode for the capacitor;  
 
 (c) a second dielectric material disposed the substrate about the intermediate portion of the first dielectric region to dielectrically isolate the node region of the trench from the second conductive material; and  
 (d) a hydrogen passivation layer disposed in the intermediate portion of the trench about portions of the second dielectric material.  
   
     
     
         17 . The method recited in  claim 1  wherein the step of treating the surface with hydrogen comprises the step of treated a selected portion of the surface with hydrogen.  
     
     
         18 . The method recited in  claim 5  wherein the step of treating the surface with hydrogen comprises the step of treated a selected portion of the surface with hydrogen.  
     
     
         19 . The method recited in  claim 8  wherein the step of treating the surface with hydrogen comprises the step of treated a selected portion of the surface with hydrogen.  
     
     
         20 . The method recited in  claim 12  wherein the step of treating the surface with hydrogen comprises the step of treated a selected portion of the surface with hydrogen.  
     
     
         21 . The method recited in  claim 1  wherein the dielectric layer forming step comprises the step of forming a LOCOS region in the silicon.  
     
     
         22 . The method recited in  claim 1  wherein the dielectric layer forming step comprises the step of forming a shallow trench isolation region in the silicon.  
     
     
         23 . The method recited in  claim 1  wherein the dielectric layer forming step comprises the step of forming such dielectric layer sidewall of a gate electrode.