Circuit and method for an integrated level shifting latch

Abstract

An integrated circuit (IC) comprising an integrated level shifting latch for I/O. The level shift in the IC I/O section may be clocked. In addition, a latch may be moved from the core section to the I/O section of the device, and thus the incoming clock may remain in the external voltage domain to clock the latch along with the level shift. The level shift and latch may be clocked on opposite phases of the clock. Preferably, the level shift and latch may operate differentially on the data signal. Both setup and clock-to-Q times are significantly reduced with respect to prior art devices, allowing higher speed industry specifications may be met.

What is claimed is:  
     
         1 . An integrated circuit (IC) having a core section and an input/output (I/O) section, said IC comprising: 
 a clocked level shifter, wherein said level shifter shifts data from a core voltage level to an I/O voltage level; and    a clocked latch coupled an output of said level shifter, wherein said latch captures said data at said I/O voltage level.    
     
     
         2 . The integrated circuit of  claim 1 , wherein said level shifter is a differential level shifter receiving differential data at said core voltage level and providing a differential data output at said I/O voltage level.  
     
     
         3 . The integrated circuit of  claim 2 , wherein said latch is a differential input latch receiving said differential data output from said differential level shifter.  
     
     
         4 . The integrated circuit of  claim 3 , wherein said latch provides a single-ended data output.  
     
     
         5 . The integrated circuit of  claim 1 , wherein an external clock received by said IC remains at said I/O voltage level for clocking said level shifter and said latch.  
     
     
         6 . The integrated circuit of  claim 1 , wherein said level shifter shifts said data on one phase of an external clock and said latch captures data on an opposite phase of said external clock.  
     
     
         7 . The integrated circuit of  claim 1 , wherein said core voltage level is 1.8 volts and said I/O voltage level is 3.3 volts.  
     
     
         8 . The integrated circuit of  claim 1 , wherein said latch is a master flip-flop of a master/slave flip-flop pair.  
     
     
         9 . The integrated circuit of  claim 1 , wherein said level shifter comprises I/O voltage level transistors coupled to core voltage level transistors, wherein gates of said I/O voltage level transistors are coupled to a clock, and wherein gates of said core voltage level transistors are coupled to said core voltage level.  
     
     
         10 . The integrated circuit of  claim 1 , wherein said IC is an application specific IC (ASIC).  
     
     
         11 . A method of providing data at an output of an integrated circuit (IC), said IC comprising a core section having a core voltage level and an I/O section having an I/O voltage level, said method comprising: 
 level shifting said data from said core voltage level to said I/O voltage level synchronous to an external clock; and    latching said data at said I/O voltage level synchronous to said external clock.    
     
     
         12 . The method of  claim 11 , further comprising level shifting said data differentially.  
     
     
         13 . The method of  claim 12 , further comprising latching said data differentially.  
     
     
         14 . The method of  claim 13 , further comprising providing a single-ended data signal to said output after said latching.  
     
     
         15 . The method of  claim 11 , wherein said external clock remains at said I/O voltage level for synchronizing said level shifting and said latching.  
     
     
         16 . The method of  claim 11 , further comprising level shifting said data on one phase of said external clock and latching said data on an opposite phase of said external clock.  
     
     
         17 . The method of  claim 11 , wherein said core voltage level is 1.8 volts and said I/O voltage level is 3.3 volts.  
     
     
         18 . An integrated circuit (IC) having a level shifter for shifting between a core voltage level and an input/output (I/O) voltage level, said IC comprising: 
 a low voltage transistor in said level shifter having a first gate and a first source/drain, wherein said first gate is connected to said core voltage level; and    a high voltage transistor in said level shifter having a second gate and a second source/drain, wherein said second source/drain is coupled to said first source/drain of said low voltage transistor, and wherein said second gate of high voltage transistor is coupled to an I/O voltage level enable signal.    
     
     
         19 . The integrated circuit of  claim 18 , wherein said level shifter is a differential level shifter.  
     
     
         20 . A method of saving power in an integrated circuit (IC) having a level shifter for shifting between a core voltage level and an input/output (I/O) voltage level, said method comprising: 
 disabling an I/O voltage level signal at a gate of a high voltage transistor in said level shifter, wherein a source/drain of said high voltage transistor is coupled to a source/drain of a low voltage transistor in said level shifter; and    after said disabling, turning off said IC's core voltage level power, wherein a gate of said low voltage transistor is coupled to said core voltage level.    
     
     
         21 . The method of claim  20 , wherein said level shifter operates differentially, and wherein gates of multiple high voltage transistors are disabled before turning off said IC's core voltage level power.