Shallow trench isolation type semiconductor device and method of forming the same

Abstract

A shallow trench isolation type semiconductor device is described, which includes a trench having a flexure in a bottom thereof. The flexure has a step difference of about 100 Å or more, and is preferably made at a middle area. Conventionally, a gate insulating layer includes a thin area of about 100 Å or less and a thick area of about 200 Å or more. On the basis of a bottom of a trench peripheral region, a middle part of the flexure may be concave or convex. Particularly, the foregoing device can effectively be applied to a self-aligned flash memory in which a width of a trench between one active region and another is about 3 micrometers or less.

What is claimed is:  
     
         1 . A shallow trench isolation type semiconductor device including: 
 at least two regions where gate insulating layers differ in thickness; and    a silicon substrate with at least one flexure trench having a step difference.    
     
     
         2 . The device as claimed in  claim 1 , wherein there is a thickness difference of about 100 Å or more between the at least two regions.  
     
     
         3 . The device as claimed in  claim 2 , wherein the flexure trench is formed at a region where a gate insulating layer has a thickness of about 200 Å or more, out of the at least two regions.  
     
     
         4 . The device as claimed in  claim 1 , wherein the silicon substrate is convex in a middle area of the flexure trench.  
     
     
         5 . The device as claimed in  claim 1 , wherein the silicon substrate is convex in one of a lower voltage part and a higher voltage part, wherein the respective flexure trenches are contacted with an active region.  
     
     
         6 . The device as claimed in  claim 1 , wherein the step difference has a range of about 100 Å to about 500 Å.  
     
     
         7 . A shallow trench isolation type flash memory device including a flexure trench with a flexure having a step difference of about 100 Å to about 500 Å in a bottom thereof.  
     
     
         8 . The device as claimed in  claim 7 , wherein the trench is formed at a high voltage part of a peripheral region.  
     
     
         9 . The device as claimed in  claim 7 , wherein the flexure trench is formed using a self-aligned process to pattern a polysilicon layer in a state that the polysilicon layer being a part of a floating gate is formed on a gate insulating layer.  
     
     
         10 . The device as claimed in  claim 7 , wherein a width of the flexure trench is about 3 micrometers or less between one active region and another, in the high voltage part of the peripheral region.  
     
     
         11 . The device as claimed in  claim 10 , wherein a silicon substrate is concave in a middle area of the flexure trench.  
     
     
         12 . A method of forming a shallow trench isolation type semiconductor device comprising the steps of: 
 forming a gate oxide layer, so that a flexure is different from adjacent parts in thickness, the flexure being a part of a trench area on a substrate;    forming an etching mask pattern to expose the gate oxide layer in the trench area; and    anisotropically and sequentially etching the gate oxide layer and a silicon substrate to form a trench, the gate oxide layer being located on the substrate where the etching mask pattern is formed.    
     
     
         13 . The method of  claim 12 , wherein the step of anisotropically and sequentially etching the gate oxide layer and the silicon substrate is performed by one etchant.  
     
     
         14 . The method of  claim 12  further comprising a step of stacking a polysilicon layer between the steps of forming the gate oxide layer and forming the etching mask pattern.  
     
     
         15 . The method of  claim 12 , wherein the semiconductor device is a flash memory.