Retrograde doping profile in twin well CMOS device

Abstract

Provided with a method of fabricating a semiconductor device including the steps of: selectively forming an insulating oxide layer in a semiconductor substrate having a first conductivity type, wherein the semiconductor substrate has first and second regions; forming impurity layers having a second conductivity type in the first and second regions of the semiconductor substrate; forming a first mask layer in the second region of the semiconductor substrate; forming impurity layers having the second conductivity type in the first region of the semiconductor substrate by performing serial ion implantations with different doses of dopants at different acceleration energies; forming a second mask layer in the first region of the semiconductor substrate; and forming impurity layers having the first conductivity type in the second region of the semiconductor substrate by performing serial ion implantations with different doses of dopants at different acceleration energies.

what is claimed is:  
     
         1 . A semiconductor device comprising: 
 a semiconductor substrate having a first conductivity type; and    twin wells formed in adjacent regions of a surface portion of the semiconductor substrate,    a first of the twin wells having a second conductivity type formed in a first portion of the semiconductor substrate such that, in a direction of depth, a junction exists between the first twin well and the semiconductor substrate, and    a second of the twin wells having the first conductivity type formed in a second portion of the semiconductor substrate such that, in a direction of depth, a junction exists between the second twin well and the semiconductor substrate, said substrate having no buried implanted layer beneath the twin wells.    
     
     
         2 . The semiconductor device as claimed in  claim 1 , wherein the first and second wells have a junction depth of 1.5 μm.  
     
     
         3 . The semiconductor device as claimed in  claim 1 , wherein three layers of ions are included in the second twin well of the semiconductor substrate.  
     
     
         4 . The semiconductor device as claimed in  claim 1 , wherein three layers of ions are included in the second twin well of the semiconductor substrate, the three layers including lower and middle layers of a retrograde well and a threshold voltage layer in the surface of the retrograde well.  
     
     
         5 . The semiconductor device as claimed in  claim 1 , wherein two layers of ions are included in the first twin well of the semiconductor substrate, the two layers including a lower layer of a retrograde well and a threshold voltage layer at the surface of the retrograde well.  
     
     
         6 . The semiconductor device of  claim 1 , wherein the twin wells are symmetric about an axis perpendicular to the surface of the substrate.  
     
     
         7 . The semiconductor device of  claim 1 , wherein the twin wells have equal depth.  
     
     
         8 . The semiconductor device as claimed in  claim 1 , wherein the first twin well extends to a predetermined depth in the semiconductor substrate, and increases in second conductivity type impurity ion concentration in the direction of depth.  
     
     
         9 . The semiconductor device as claimed in  claim 1 , wherein the second twin well extends to a predetermined depth in the semiconductor substrate, and increases in first conductivity type impurity ion concentration in the direction of depth.