3-D smart power IC

Abstract

An integrated smart power circuit including a power semiconductor device fabricated on a conducting substrate with a source positioned adjacent the upper surface of the substrate, a control terminal between the upper and lower surfaces, and a drain positioned adjacent the lower surface of the substrate. A high resistance layer is formed on a portion of the upper surface of the substrate, either directly overlying or adjacent to the power device, and doped semiconductor material is positioned on the high resistance layer. Control circuitry is formed in the doped semiconductor material. The high resistance layer can be conveniently formed by growing a layer of AlAs and growing doped layers on the AlAs. The AlAs can be easily oxidized thereafter.

What is claimed is:  
     
         1 . An integrated smart power circuit comprising: 
 a conducting substrate having an upper and a lower surface;    a power semiconductor device fabricated on the substrate and including a first current carrying terminal positioned adjacent the upper surface of the substrate, a control terminal, and a second current carrying terminal positioned adjacent the lower surface of the substrate;    a high resistance layer formed on a portion of the upper surface of the substrate;    doped semiconductor material positioned on the high resistance layer; and    control circuitry formed in the doped semiconductor material.    
     
     
         2 . An integrated smart power circuit as claimed in  claim 1  wherein the substrate includes GaAs.  
     
     
         3 . An integrated smart power circuit as claimed in  claim 1  wherein the power semiconductor device includes a vertical field effect transistor with the first current carrying terminal being a source terminal, the control terminal being a gate terminal, and the second current carrying terminal being a drain terminal.  
     
     
         4 . An integrated smart power circuit as claimed in  claim 1  wherein the high resistance layer includes one of a nitride, an oxide, and an amorphous material.  
     
     
         5 . An integrated smart power circuit as claimed in  claim 4  wherein the high resistance layer includes aluminum oxide.  
     
     
         6 . An integrated smart power circuit as claimed in  claim 5  wherein the aluminum oxide includes a layer of oxidized AlAs deposited on a gallium arsenide substrate.  
     
     
         7 . An integrated smart power circuit as claimed in  claim 4  wherein the high resistance layer includes low temperature gallium arsenide deposited on a gallium arsenide substrate.  
     
     
         8 . An integrated smart power circuit as claimed in  claim 1  wherein the high resistance layer and the doped semiconductor material with the control circuitry formed therein are positioned in overlying relationship to at least a portion of the power semiconductor device.  
     
     
         9 . An integrated smart power circuit as claimed in  claim 1  wherein the control circuitry includes a plurality of lateral field effect transistors.  
     
     
         10 . An integrated smart power circuit comprising: 
 a conducting gallium arsenide substrate having an upper and a lower surface;    a vertical power transistor fabricated on the substrate and including a first current carrying terminal positioned adjacent the upper surface of the substrate, a gate terminal, and a second current carrying terminal positioned adjacent the lower surface of the substrate;    a high resistance layer formed on a portion of the upper surface of the substrate, the high resistance layer including one of aluminum oxide and low temperature gallium arsenide;    doped semiconductor material positioned on the high resistance layer; and    control circuitry, including a plurality of lateral field effect transistors, formed in the doped semiconductor material.    
     
     
         11 . An integrated smart power circuit as claimed in  claim 10  wherein the aluminum oxide includes a layer of oxidized AlAs deposited on the gallium arsenide substrate.  
     
     
         12 . An integrated smart power circuit as claimed in  claim 10  wherein the high resistance layer and the doped semiconductor material with the control circuitry formed therein are positioned in overlying relationship to at least a portion of the power semiconductor device.  
     
     
         13 . A method of fabricating an integrated smart power circuit comprising the steps of: 
 providing a conducting substrate with an upper and a lower surface;    forming a vertical power semiconductor device on the substrate and positioning a first current carrying terminal adjacent the upper surface of the substrate and a second current carrying terminal adjacent the lower surface of the substrate;    forming a high resistance layer on a portion of the upper surface of the substrate;    providing doped semiconductor material on the high resistance layer; and    forming control circuitry in the doped semiconductor material.    
     
     
         14 . A method of fabricating an integrated smart power circuit as claimed in  claim 13  wherein the step of forming a vertical power semiconductor device includes positioning gate material between the upper and lower surfaces of the substrate.  
     
     
         15 . A method of fabricating an integrated smart power circuit as claimed in  claim 13  wherein the steps of forming a high resistance layer and providing doped semiconductor material include epitaxially growing a layer of AlAs on the substrate, epitaxially growing doped semiconductor layers on the AlAs, and oxidizing the AlAs either before or after the step of forming control circuitry in the doped semiconductor material  
     
     
         16 . A method of fabricating an integrated smart power circuit as claimed in  claim 15  wherein the steps of epitaxially growing the layer of AlAs on the substrate, epitaxially growing doped semiconductor layers on the AlAs, and oxidizing the AlAs include providing oxidation vias through the doped semiconductor layers so as to enhance oxidizing the AlAs.  
     
     
         17 . A method of fabricating an integrated smart power circuit as claimed in  claim 16  wherein the step of providing oxidation vias includes providing holes with approximately a 10 μm diameter through the doped semiconductor layers at approximately 100 μm intervals.  
     
     
         18 . A method of fabricating an integrated smart power circuit as claimed in  claim 13  wherein the steps of forming a high resistance layer and providing doped semiconductor material include growing a low temperature GaAs layer on the substrate, growing an AlGaAs buffer layer on the low temperature GaAs layer, and growing a GaAs layer on the AlGaAs buffer layer.  
     
     
         19 . A method of fabricating an integrated smart power circuit as claimed in  claim 13  wherein the steps of forming the high resistance layer includes forming the high resistance layer in overlying relationship to at least a portion of the vertical power semiconductor device