Bipolar transistor and method for fabricating the same

Abstract

An n-type first single crystal silicon layer is provided as collector region over a silicon substrate with a first insulating film interposed therebetween. A p-type first polysilicon layer is provided as an extension of a base region over the first single crystal silicon layer with a second insulating film interposed therebetween. A p-type second single crystal silicon layer is provided as intrinsic base region on a side of the first single crystal silicon layer, second insulating film and first polysilicon layer. An n-type third single crystal silicon layer is provided as emitter region on a side of the second single crystal silicon layer. And an n-type third polysilicon layer is provided on the first insulating film as extension of an emitter region and is connected to a side of the third single crystal silicon layer.

What is claimed is:  
     
         1 . A method for fabricating a bipolar transistor, comprising the steps of: 
 forming a first semiconductor layer of a first conductivity type, an insulating film and a second semiconductor layer of a second conductivity type in this order over a semiconductor substrate;    forming a third semiconductor layer of the second conductivity type on respective side faces of the first and second semiconductor layers and the insulating film;    forming a fourth semiconductor layer of the first conductivity type on a side of the third semiconductor layer, the side being opposite to the other side of the third semiconductor layer that is in contact with the first and second semiconductor layers;    forming a fifth semiconductor layer of the first conductivity type over the semiconductor substrate such that the fifth semiconductor layer is in contact with the fourth semiconductor layer; and    defining the third semiconductor layer as a base region, the first semiconductor layer as one of collector and emitter regions, the fourth semiconductor layer as the other of the collector and sitter regions, the second semiconductor layer as an extension of the third semiconductor layer and the fifth semiconductor layer as an extension of the fourth semiconductor layer, respectively.    
     
     
         2 . The method of  claim 1 , wherein the area of the second semiconductor layer is smaller than that of the first semiconductor layer.  
     
     
         3 . The method of  claim 1  wherein the first and fourth semiconductor layers are silicon layers, and 
 wherein the third semiconductor layer is a silicon germanium layer.  
 
     
     
         4 . The method of  claim 1 , wherein the steps of forming the fourth and fifth semiconductor layers are performed as a single process step.