Self-aligned damascene interconnect

Abstract

A structure and method for a capacitor-over-bitline integrated circuit device includes forming a device on a substrate, forming a capacitor contact electrically connected to the device, forming a bitline trench using the capacitor contact to align the bitline trench, forming insulating spacers in the bitline trench, forming a conductive bitline in the trench, the bitline being electrically connected to the device, forming an inter-layer dielectric over the bitline, and forming a capacitor above the inter-layer dielectric, such that the capacitor is electrically connected to the capacitor contact.

Having thus described our invention, what we claim as new and desire to secure by letters patent is as follows:  
     
         1 . A method of manufacturing a capacitor-over-bitline integrated circuit device comprising: 
 forming a device on a substrate;    forming a capacitor contact electrically connected to said device;    forming a bitline trench using said capacitor contact to align said bitline trench;    forming insulating spacers in said bitline trench;    forming a conductive bitline in said trench, said bitline being electrically connected to said device;    forming an inter-layer dielectric over said bitline; and    forming a capacitor above said inter-layer dielectric, such that said capacitor is electrically connected to said capacitor contact.    
     
     
         2 . The method in  claim 1 , wherein said forming of said insulating spacers includes forming one of said insulating spacers on said capacitor contact.  
     
     
         3 . The method in  claim 1 , wherein said forming of said capacitor contact includes forming a cap above said capacitor contact, wherein said cap protects said capacitor contact during said forming of said bitline trench and said cap aligns said bitline trench with said capacitor contact.  
     
     
         4 . The method in  claim 1 , wherein said forming of said bitline comprises depositing a conductive material in said bitline trench using a damascene process.  
     
     
         5 . The method in  claim 1 , wherein said forming of said device comprises forming a field effect transistor.  
     
     
         6 . The method in  claim 1 , wherein a size of said capacitor contact is unaffected by said insulating spacers.  
     
     
         7 . A method of manufacturing a multilevel interconnection comprising: 
 forming a device;    forming a contact electrically connected to said device;    forming a trench using said contact to align said trench;    forming spacers in said trench;    forming a first conductor in said trench, said first conductor being electrically connected to said device;    forming an insulator over said first conductor; and    forming a second conductor above said insulator, such that said second conductor is electrically connected to said contact.    
     
     
         8 . The method in  claim 7 , wherein said forming of said spacers includes forming one of said spacers on said contact.  
     
     
         9 . The method in  claim 7 , wherein said forming of said contact includes forming a cap above said contact, wherein said cap protects said contact during said forming of said trench and said cap aligns said trench with said contact.  
     
     
         10 . The method in  claim 7 , wherein said forming of said first conductor comprises depositing a conductive material in said trench using a damascene process.  
     
     
         11 . The method in  claim 7 , wherein said forming of said device comprises forming a field effect transistor.  
     
     
         12 . The method in  claim 7 , wherein a size of said contact is unaffected by said spacers.  
     
     
         13 . A multilevel interconnection device comprising: 
 a contact;    a trench adjacent said contact, wherein said contact aligns said trench;    insulating spacers lining walls of said trench;    a conductive line in said trench,    an inter-layer dielectric over said line; and    a device above said inter-layer dielectric, wherein said device is electrically connected to said contact.    
     
     
         14 . The device in  claim 13 , wherein one of said insulating spacers is on said contact.  
     
     
         15 . The device in  claim 13 , further comprising a cap above said contact, wherein said cap protects said contact during forming of said trench and said cap aligns said trench with said capacitor contact.  
     
     
         16 . The device in  claim 13 , wherein said conductive line is formed using a damascene process.  
     
     
         17 . The device in  claim 13 , wherein said device comprises a field effect transistor electrically connected to a capacitor by said contact.  
     
     
         18 . The device in  claim 13 , wherein a size of said contact is unaffected by said insulating spacers.  
     
     
         19 . A method of manufacturing a multilevel interconnection comprising: 
 forming a first wiring level;    forming a first insulator over said first wiring level;    forming a contact electrically connected to said first wiring level;    forming a trench in said insulator using said contact to align said trench;    forming spacers in said trench;    forming an intermediate wiring level in said trench;    forming an insulator over said intermediate wiring level; and    forming a second wiring level above said insulator, such that said second wiring level is electrically connected to said contact.    
     
     
         20 . The method in  claim 19 , wherein said forming of said spacers includes forming one of said spacers on said contact.  
     
     
         21 . The method in  claim 19 , wherein said forming of said contact includes forming a cap above said contact, wherein said cap protects said contact during said forming of said trench and said cap aligns said trench with said contact.  
     
     
         22 . The method in  claim 19 , wherein said forming of said intermediate wiring level comprises depositing a conductive material in said trench using a damascene process.  
     
     
         23 . The method in  claim 19 , wherein a size of said contact is unaffected by said spacers.