Method of wafer level burn-in

Abstract

The present invention relates to a system and method for performing reliability screening on semi-conductor wafers and particularly to a highly planar burn in apparatus and method for uses including wafer level burn-in (WLBI), diced die burn-in (DDBI), and packaged die burn-in (PDBI). The burn-in system includes a burn-in substrate with a planar base, a temporary Z-axis connecting member, and a Z-axis wafer level contact sheet electrically coupled to one another for screening wafers, diced die, and packaged electronic components, their assembly and use.

1 . A method of burn-in screening of electronic components comprising: 
 contacting a semiconductor wafer with a burn-in unit having a base member with a planarity of less than about 0.01 inches per linear foot and a coefficient of thermal expansion that matches the coefficient of thermal expansion of the wafer; and    generating a test signal and conveying said test signal through said burn-in unit to conductive pads on said wafer under elevated temperatures.    
     
     
         2 . The method according to  claim 1 , wherein said burn-in is conducted at a temperature of at least about 125° C.  
     
     
         3 . The method according to  claim 1 , wherein said burn-in is conducted at a temperature of at least about 150° C.  
     
     
         4 . The method according to  claim 1 , wherein said burn-in is conducted at a temperature between about 125° C. and 200° C.  
     
     
         5 . The method according  claim 1 , comprising burn-in screening semiconductor wafers that are between about 75 mm and 300 mm in diameter.  
     
     
         6 . The method according to  claim 1 , comprising burn-in screening semiconductor wafers between about 150 mm and 200 mm in diameter.  
     
     
         7 . The method according to  claim 1 , comprising burn-in screening semiconductor wafers between about 200 mm and 300 mm in diameter.  
     
     
         8 . A method of burn-in screening of electronic components comprising: 
 contacting conductive bumps of a high planarity burn-in system with conductive pads of an electronic component, said bumps being uniformly configured and having a substantially planar tip; and    generating a test signal and conveying said test signal through said conductive bumps to said conductive pads on said electronic component.    
     
     
         9 . The method according to  claim 8 , comprising burn-in screening semiconductor wafers between about 75 mm and 300 mm in diameter.  
     
     
         10 . The method according to  claim 8 , comprising burn-in screening semiconductor wafers between about 200 mm and 300 mm in diameter.  
     
     
         11 . The method according to  claim 9 , wherein said burn-in is conducted at a temperature of at least about 125° C.  
     
     
         12 . The method according to  claim 9 , wherein said burn-in is conducted at a temperature of at least about 150° C.  
     
     
         13 . The method according to  claim 9 , wherein said burn-in is conducted at a temperature between about 125° C. and 200° C.  
     
     
         14 . The method according to  claim 9 , wherein a bump tip of between about 10 μm to 50 μm in diameter contacts said conductive pads.