Nonvolatile semiconductor memory device and method of manufacturing the same

Abstract

A nonvolatile semiconductor memory device includes an n-type region which is in contact with n + drain diffusion region at a surface of p-type silicon substrate and covers the periphery thereof. The device also includes a p-type impurity region which is in contact with n-type region and covers the periphery thereof. The n + drain diffusion region, n-type region and p + impurity region extend to region located immediately under the floating gate electrode. Thereby, the nonvolatile semiconductor memory device has a structure which can promote injection of high energy electrons along a gate electrode direction.

What is claimed is:  
     
         1 . A nonvolatile semiconductor memory device allowing electrical erasing and writing of data comprising: 
 a semiconductor substrate of a first conductivity type having a main surface;    a charge accumulating electrode layer formed on the main surface of said semiconductor substrate with a first insulating film therebetween;    a control electrode layer formed on said charge accumulating electrode layer with a second insulating film therebetween;    a pair of source/drain regions of a second conductivity type formed at the main surface of said semiconductor substrate and located at opposite sides of a region of said semiconductor substrate located under said charge accumulating electrode layer;    said drain region extending to a region of said semiconductor substrate located immediately under said charge accumulating electrode layer;    a first impurity region of the second conductivity type located to be in contact with said drain region at the main surface of said semiconductor substrate located immediately under said charge accumulating electrode layer, and having an impurity concentration lower than that of said drain region; and    a second impurity region of the first conductivity type being in contact with said first impurity region at the main surface of said semiconductor substrate located immediately under said charge accumulating electrode layer, and having an impurity concentration higher than that of said semiconductor substrate.    
     
     
         2 . The nonvolatile semiconductor memory device according to  claim 1 , wherein said second impurity region is spaced from said source region by a distance.  
     
     
         3 . The nonvolatile semiconductor memory device according to  claim 2 , wherein said first impurity region covers the periphery of said drain region while being in contact with said drain region.  
     
     
         4 . The nonvolatile semiconductor memory device according to  claim 2 , further comprising a third impurity region of the first conductivity type covering peripheries of said source region and said second impurity region while being in contact with said source region and said second impurity region, and having an impurity concentration higher than that of said semiconductor substrate and lower than that of said second impurity region.  
     
     
         5 . The nonvolatile semiconductor memory device according to  claim 2 , further comprising a third impurity region of the second conductivity type formed in at least one of said drain region and said source region having an impurity concentration higher than that of said drain region and said source region.  
     
     
         6 . The nonvolatile semiconductor memory device according to  claim 2 , wherein a depth of said second impurity region from the main surface of said semiconductor substrate is smaller than that of said first impurity region.  
     
     
         7 . The nonvolatile semiconductor memory device according to  claim 2 , further comprising a third impurity region covering a periphery of said source region while being in contact with said source region, extending to a region of said semiconductor substrate immediately under said charge accumulating electrode layer, and having an impurity concentration lower than that of said source region.  
     
     
         8 . The nonvolatile semiconductor memory device according to  claim 7 , wherein said source region and said drain region have different depths from the main surface of said semiconductor substrate.  
     
     
         9 . The nonvolatile semiconductor memory device according to  claim 7 , wherein said source region and said drain region have different impurity concentrations.  
     
     
         10 . The nonvolatile semiconductor memory device according to  claim 7 , wherein said third impurity region and said drain region have different depths from the main surface of said semiconductor substrate.  
     
     
         11 . The nonvolatile semiconductor memory device according to  claim 7 , wherein said third impurity region and said drain region have different impurity concentrations.  
     
     
         12 . The nonvolatile semiconductor memory device according to  claim 1 , wherein said second impurity region is in contact with said source region at the main surface of said semiconductor substrate directly below said charge accumulating electrode layer.  
     
     
         13 . The nonvolatile semiconductor memory device according to  claim 12 , wherein 
 said device further comprises a third impurity region of the first conductivity type covering said first impurity region while being in contact with said first impurity region, and having an impurity concentration lower than that of said semiconductor substrate, and    said third impurity region exists between said second impurity region and said first impurity region.    
     
     
         14 . A nonvolatile semiconductor memory device allowing electrical erasing and writing of data comprising: 
 a semiconductor substrate of a first conductivity type having a main surface;    a charge accumulating electrode layer formed on the main surface of said semiconductor substrate with a first insulating film therebetween;    a control electrode layer formed on said charge accumulating electrode layer with a second insulating film therebetween;    a pair of source/drain regions of a second conductivity type formed at the main surface of said semiconductor substrate, and located at opposite sides of a region of said semiconductor substrate located under said charge accumulating electrode layer;    said drain region extending to a region of said semiconductor substrate located immediately under said charge accumulating electrode layer, and containing impurity at a concentration of 1×10 20 cm −3  or more;    a first impurity region covering a periphery of said drain region while being in contact with said drain region, and having an impurity concentration larger than that of said semiconductor substrate; and    a second impurity region of the first conductivity type formed to be in contact with said source region and said first impurity region at a region of said semiconductor substrate located immediately under said charge accumulating electrode layer, and having an impurity concentration higher than that of said semiconductor substrate and lower than that of said first impurity region.    
     
     
         15 . The nonvolatile semiconductor memory device according to  claim 14 , wherein a depth of said second impurity region from the main surface of said semiconductor substrate is smaller than that of said source/drain regions.  
     
     
         16 . The nonvolatile semiconductor memory device according to  claim 14 , wherein said second impurity region covers peripheries of said source region and said first impurity region while it is in contact with said source region and said first impurity region.  
     
     
         17 . The nonvolatile semiconductor memory device according to  claim 1 , wherein said first impurity region is in contact with and surrounding said drain region, and said second impurity region covers peripheries of said source region and said first impurity region.  
     
     
         18 . A method of manufacturing a nonvolatile semiconductor memory device allowing electrical erasing and writing of data comprising the steps of: 
 forming a charge accumulating electrode layer on a main surface of a semiconductor substrate of a first conductivity type with a first insulating layer therebetween, and a control electrode layer on said charge accumulating electrode layer with a second insulating film therebetween;    forming a pair of source/drain regions of a second conductivity type at the main surface of said semiconductor substrate, said pair of source/drain regions being located at opposite sides of a region of said semiconductor substrate located immediately under said charge accumulating electrode layer;    said drain region extending to a region of said semiconductor substrate located immediately under said charge accumulating electrode layer;    forming a first impurity region of the second conductivity type to be in contact with said drain region and to have an impurity concentration lower than that of said drain region at the main surface of said semiconductor substrate located immediately under said charge accumulating electrode layer; and    forming a second impurity region of the first conductivity type to be in contact with said first impurity region and to have an impurity concentration higher than that of said semiconductor substrate at the main surface of said semiconductor substrate located immediately under said charge accumulating electrode layer.    
     
     
         19 . The method of manufacturing the nonvolatile semiconductor memory device according to  claim 18 , wherein 
 said step of forming said source region includes the step of implanting impurity of the second conductivity type with a first mask disposed on a drain formation region in said semiconductor substrate,    said step of forming said drain region includes the step of implanting impurity of the second conductivity type with a second mask disposed on a source formation region in said semiconductor substrate,    said step of forming said first impurity region includes the step of implanting impurity of the second conductivity type using said second mask, and    said step of forming said second impurity region includes the step of implanting impurity of the first conductivity type in a direction tilted with respect to the main surface of said semiconductor substrate using said second mask.    
     
     
         20 . The method of manufacturing the nonvolatile semiconductor memory device according to  claim 18 , wherein 
 said method further comprises the step of forming a third impurity region of the first conductivity type surrounding peripheries of said source region and said second impurity region while being in contact with said source region and said second impurity region, and having an impurity concentration higher than that of said semiconductor substrate and lower than that of said second impurity region, and    said step of forming said third impurity region includes the step of implanting impurity of the first conductivity type into said semiconductor substrate before forming said charge accumulating electrode layer and said control electrode layer.    
     
     
         21 . The method of manufacturing the nonvolatile semiconductor memory device according to  claim 18 , further comprising the steps of: 
 forming a side wall insulating layer covering side walls of said charge accumulating electrode layer and said control electrode layer,    forming a third impurity region of the first conductivity type in said drain region, said third impurity region having an impurity concentration higher than that of said drain region, and    forming a fourth impurity region of the second conductivity type in said source region, said fourth impurity region having an impurity concentration higher than that of said source region, wherein    said steps of forming said third and fourth impurity regions include the steps of implanting impurity of the second conductivity type into the main surface of said semiconductor substrate using said side wall insulating layer as a mask.    
     
     
         22 . The method of manufacturing the nonvolatile semiconductor memory device according to  claim 18 , wherein 
 said second impurity region is formed only at a region of said semiconductor substrate immediately under said charge accumulating electrode layer and is in contact with portions of said source region and said first impurity region located immediately under said charge accumulating electrode layer, and    said step of forming said second impurity region includes the step of selectively implanting impurity of the first conductivity type only into a region of said semiconductor substrate immediately under said charge accumulating electrode layer before formation of said charge accumulating electrode layer and said control electrode layer.    
     
     
         23 . The method of manufacturing the nonvolatile semiconductor memory device according to  claim 18 , wherein 
 said second impurity region is formed to be in contact with portions of said source region and said first impurity region located immediately under said charge accumulating electrode layer only at a region of said semiconductor substrate immediately under said charge accumulating electrode layer, and    said step of forming said second impurity region includes the steps of:    implanting impurity of the first conductivity type into the whole surface of said semiconductor substrate before formation of said charge accumulating electrode layer and said control electrode layer, and    implanting impurity of the second conductivity type into a region other than a region of said semiconductor substrate immediately under said charge accumulating electrode layer, using said charge accumulating electrode layer and said control electrode layer as a mask.    
     
     
         24 . A method of manufacturing a nonvolatile semiconductor memory device allowing electrical erasing and writing of data comprising the steps of: 
 forming a charge accumulating electrode layer on a main surface of a semiconductor substrate of a first conductivity type with a first insulating layer therebetween, and a control electrode layer on said charge accumulating electrode layer with a second insulating film therebetween;    forming a pair of source/drain regions of a second conductivity type at the main surface of said semiconductor substrate, said pair of source/drain regions being located at opposite sides of a region of said semiconductor substrate located immediately under said charge accumulating electrode layer;    said drain region extending to a region of said semiconductor substrate located immediately under said charge accumulating electrode layer;    forming a first impurity region of the second conductivity type at the main surface of said semiconductor substrate located immediately under said charge accumulating electrode layer, said first impurity region being in contact with said drain region and having an impurity concentration lower than that of said drain region; and    forming a second impurity region of the first conductivity type to be in contact with said source region and said first impurity region and to have an impurity concentration higher than that of said semiconductor substrate at a region of said semiconductor substrate located immediately under said charge accumulating electrode layer.    
     
     
         25 . The method of manufacturing the nonvolatile semiconductor memory device according to  claim 24 , wherein 
 said step of forming said second impurity region includes the step of implanting impurity of the first conductivity into the main surface of said semiconductor substrate before forming said charge accumulating electrode layer and said control electrode layer,    said step of forming said source region includes the step of implanting impurity of the second conductivity type with a first mask disposed on a drain formation region in said semiconductor substrate,    said step of forming said drain region includes the step of implanting impurity of the second conductivity type with a second mask disposed on a source formation region in said semiconductor substrate, and    said step of forming said first impurity region includes the step of implanting impurity of the second conductivity type using said second mask.    
     
     
         26 . A method of manufacturing a nonvolatile semiconductor memory device allowing electrical erasing and writing of data comprising the steps of: 
 forming a charge accumulating electrode layer on a main surface of a semiconductor substrate of a first conductivity type with a first insulating layer therebetween, and a control electrode layer on said charge accumulating electrode layer with a second insulating film therebetween;    forming a pair of source/drain regions of a second conductivity type at the main surface of said semiconductor substrate, said pair of source/drain regions being located at opposite sides of a region of said semiconductor substrate located immediately under said charge accumulating electrode layer;    said drain region extending to a region of said semiconductor substrate located immediately under said charge accumulating electrode layer, and having an impurity concentration of 1×10 20 cm −3    3  or more;    forming a first impurity region of the first conductivity type covering said drain region while being in contact with said drain region and having an impurity concentration higher than that of said semiconductor substrate; and    forming a second impurity region of the first conductivity type to be in contact with said source region and said first impurity region and to have an impurity concentration higher than that of said semiconductor substrate and lower than that of said first impurity region at a region of said semiconductor substrate located immediately under said charge accumulating electrode layer.    
     
     
         27 . The method of manufacturing the nonvolatile semiconductor memory device according to claim  30 , wherein 
 said step of forming said second impurity region includes the step of implanting impurity of the first conductivity type into the main surface of said semiconductor substrate before forming said charge accumulating electrode layer and said control electrode layer,    said step of forming said source region includes the step of implanting impurity of the second conductivity type with a first mask disposed on a drain formation region in said semiconductor substrate,    said step of forming said drain region includes the step of implanting impurity of the second conductivity type with a second mask disposed on a source formation region in said semiconductor substrate, and    said step of forming said first impurity region includes the step of implanting impurity of the first conductivity type in a direction tilted with respect to the main surface of said semiconductor substrate using said second mask.