Power rectifier device and method of fabricating power rectifier devices

Abstract

A power rectifier having low on resistance, mass recovery times and low forward voltage drop. In a preferred embodiment, the present invention provides a power rectifier device employing a vertical device structure, i.e., with current flow between the major surfaces of the discrete device. The device employs a large number of parallel connected cells, each comprising a MOSFET structure with a gate to drain short via a common metallization. This provides a low V f path through the channel regions of the MOSFET cells to the source region on the other side of the integrated circuit. A thin gate structure is formed annularly around the pedestal regions on the upper surface of the device and a precisely controlled body implant defines the channel region and allows controllable device characteristics, including gate threshold voltage and V f . A parallel Schottky diode is also provided which increases the switching speed of the MOSFET cells. The present invention further provides a method for manufacturing a rectifier device which provides highly repeatable device characteristics and which can provide such devices at reduced cost. The active channel regions of the device are defined using pedestals in a double spacer, double implant self-aligned process. The channel dimensions and doping characteristics may be precisely controlled despite inevitable process variations in spacer sidewall formation. Only two masking steps are required, reducing processing costs.

What is claimed is:  
     
         1 . A rectifier device, comprising: 
 a semiconductor substrate having a first major surface and a second major surface;    a plurality of active cells on the first major surface;    first and second electrical contacts on the first and second major surfaces, respectively, which define a current flow path vertically between the major surfaces through the plurality of active cells; and    a plurality of Schottky diode regions on the first major surface adjacent respective active cell regions and defining parallel current flow paths between said first and second major surfaces.    
     
     
         2 . A rectifier device as set out in  claim 1 , wherein each Schottky diode comprises a Schottky metal layer in direct contact with said semiconductor substrate.  
     
     
         3 . A rectifier device as set out in  claim 1 , wherein said active cells are annular in shape and wherein said Schottky diodes are configured within the annular active cells.  
     
     
         4 . A rectifier device as set out in  claim 3 , wherein said active cells are rectangular in shape.  
     
     
         5 . A rectifier device as set out in  claim 3 , wherein said active cells each comprise a channel region, a gate oxide and a gate over said gate oxide and wherein the current flow through the active cell flows through the channel region under control of the potential applied to the gate.  
     
     
         6 . A rectifier device as set out in  claim 5 , wherein said active cells further comprise a highly doped drain contact region adjacent the channel and wherein the drain region and the gate are electrically shorted by a conductive layer.  
     
     
         7 . A rectifier device as set out in  claim 6 , wherein said active cells further comprise a body region underlying said channel region and of opposite conductivity from said contact region.  
     
     
         8 . A rectifier device as set out in  claim 2 , wherein said Schottky metal is composed of Ti, TiSi 2 , molybdenum, aluminum, platinum, suicides of molybdenum, aluminum or platinum, or any other metals or their silicide capable of forming a Schottky barrier with Si.  
     
     
         9 . A rectifier device as set out in  claim 6 , wherein said highly doped contact region is doped to about 10 19 -10 21  cm −3  of an N type dopant.  
     
     
         10 . A rectifier, comprising: 
 a MOSFET device configured as an integrated circuit on a semiconductor substrate having first and second surfaces and having a source region on one surface and a plurality of MOSFET cells on the other surface for controlling current flow between the two surfaces, each MOSFET cell having a gate, a channel and a drain and an electrically conductive layer shorting the gate and drain; and    a plurality of Schottky diodes configured adjacent respective MOSFET cells and providing a parallel current flow path to said source region.    
     
     
         11 . A rectifier as set out in  claim 10 , wherein each Schottky diode comprises a Schottky metal layer in direct contact with said semiconductor substrate.  
     
     
         12 . A rectifier as set out in  claim 11 , wherein said MOSFET cells are annular in shape and wherein said Schottky diodes are configured within the annular MOSFET cells.  
     
     
         13 . A rectifier as set out in  claim 11 , wherein the Schottky diodes are equal in number to said MOSFET cells.  
     
     
         14 . A rectifier as set out in  claim 10 , wherein the number of said MOSFET cells is from 10 to 20 million per centimeter 2 .  
     
     
         15 . A rectifier as set out in  claim 10 , wherein the gates of said MOSFET cells comprise a highly doped Polysilicon layer.  
     
     
         16 . A rectifier as set out in  claim 15 , wherein said polysilicon layer is from 200 to 1,000 Å thick.  
     
     
         17 . A rectifier as set out in  claim 12 , wherein each said Schottky diode is formed within an open region of silicon surrounded by annular sidewalls.  
     
     
         18 . A rectifier as set out in  claim 17 , wherein said gate of said MOSFET cells comprises a thin conductive layer formed on an outer surface of said sidewalls.  
     
     
         19 . A method of fabricating a rectifier device, comprising the steps of: providing a semiconductor substrate having a top and bottom surface; 
 forming a plurality of pedestals on said top surface of the semiconductor substrate;    forming a gate oxide on the substrate adjacent the pedestals;    forming a gate layer on top of said gate oxide;    forming a first spacer adjacent said pedestal sidewalls;    performing a first implant into said semiconductor substrate of a dopant of a first conductivity type, the implant being laterally defined by said first spacer;    removing the first spacer;    forming a second spacer adjacent said pedestal sidewalls, said second spacer being thicker than said first spacer;    performing a second implant into said semiconductor substrate of a dopant of a second conductivity type, said second implant being laterally defined by said second spacer;    wherein said first and second implants define a plurality of channel regions adjacent said pedestals and below said gate oxide; and    forming first and second electrical contact layers on said top and bottom surfaces, respectively, to provide a current flow path between said surfaces.    
     
     
         20 . A method as set out in  claim 19 , further comprising the step, before said step of forming a second spacer, of removing said first spacer.  
     
     
         21 . A method as set out in  claim 20 , wherein said first spacer is SiO 2 .  
     
     
         22 . A method as set out in  claim 21 , wherein said step of removing said first spacer comprises a selective SiO 2  etching step.  
     
     
         23 . A method as set out in  claim 19 , wherein said step of forming a gate comprises forming a layer of polysilicon and implanting said polysilicon with dopant of said second conductivity type.  
     
     
         24 . A method as set out in  claim 23 , wherein said polysilicon gate layer is from 200 to 1,000 Å thick.  
     
     
         25 . A method as set out in  claim 24 , wherein said polysilicon gate layer is about 500 Å thick and wherein said dopant concentration implanted into said gate is about 10 17 -10 21  cm −3 .  
     
     
         26 . A method as set out in  claim 19 , further comprising the step, prior to said second implanting step, of anisotropically etching the horizontal portion of said second spacer and underlying gate oxide to the underlying semiconductor substrate.  
     
     
         27 . A method as set out in  claim 19 , wherein the peak dopant concentration formed by said second implanting step is about 10 19 -10 21  cm −3 .  
     
     
         28 . A method as in  claim 19 , wherein said first dopant is boron and said second dopant is arsenic.  
     
     
         29 . A method as set out in  claim 19 , further comprising the steps of: 
 selectively removing said pedestal regions to expose the underlying semiconductor substrate; and    depositing a layer of a metal on said semiconductor substrate in said exposed pedestal regions to form a plurality of Schottky diode regions.    
     
     
         30 . A method as in  claim 29 , wherein said metal is molybdenum, aluminum or platinum.  
     
     
         31 . A method as set out in  claim 29 , further comprising the steps, prior to said selective pedestal removal step, of depositing a layer of titanium over the exposed surfaces, thermally processing the titanium to form titanium silicide on the exposed surfaces other than the pedestals, and selectively etching away the unconverted titanium to expose the underlying pedestals.  
     
     
         32 . A method as set out in  claim 31 , wherein said step of removing the pedestals comprises selectively etching SiO 2 .  
     
     
         33 . A method as set out in  claim 19 , further comprising the step of depositing a conductive layer over said second implanted regions and said gates to provide an electrical short therebetween.  
     
     
         34 . A method as set out in  claim 33 , wherein said conductive layer is a metal layer.  
     
     
         35 . A method as set out in  claim 19 , wherein said second spacer is comprised of polysilicon.  
     
     
         36 . A method as set out in  claim 19 , wherein said second spacer is about 5-100 times thicker than said first spacer.  
     
     
         37 . A method as set out in  claim 36 , wherein said second spacer is abut 5 microns thick and said first spacer is about 2,000 Å thick.  
     
     
         38 . A method as set out in  claim 19 , further comprising the step, prior to said step of pedestal formation, of forming a plurality of plug implants and guard ring implants of said first conductivity type in respective plug and guard ring regions.  
     
     
         39 . A method as set out in  claim 38 , wherein said plug and guard ring implant steps provide peak concentrations of about 10 15 -10 16  cm −3 .  
     
     
         40 . A method as in  claim 38 , wherein a single masking step is employed to form said plug and guard ring regions.  
     
     
         41 . A method as set out in  claim 39 , wherein said plug and guard ring implant steps further comprise a shallow implant of about 10 17 -10 19  cm −3    
     
     
         42 . A method as set out in  claim 19 , further comprising the steps of: 
 providing one or more intermediate removable spacers; and    providing additional implants of the dopant of the first conductivity type for the purpose of specific shaping of the resulting p/n junction.