Semiconductor memory device production method

Abstract

In a semiconductor memory device production method for a semiconductor memory device having a capacitor formed by a high dielectric insulation film and a noble metal upper electrode successively formed on a noble metal lower electrode, the formation of the capacitor is followed by anneal in a gas mixture atmosphere of oxygen concentration of 0 to 5% and nitrogen at temperature of 300 to 400 degrees C. This enables to reduce the leak current at room temperature and suppress leak current increase during a high temperature operation.

What is claimed is:  
     
         1 . A semiconductor memory device production method for a semiconductor memory device having a capacitor formed by a high dielectric insulation film and a noble metal upper electrode which are successively layered on a noble metal lower electrode, the method being characterized in that the formation of the capacitor is followed by anneal in a nitrogen atmosphere of 1 atmospheric pressure at temperature of 300 to 400 degrees C.  
     
     
         2 . A semiconductor memory device production method for a semiconductor memory device having a capacitor formed by a high dielectric insulation film and a noble metal upper electrode which are successively layered on a noble metal lower electrode, the method being characterized in that the formation of the capacitor is followed by anneal in a gas mixture atmosphere of oxygen concentration of 5% or below and nitrogen under 1 atmospheric pressure at temperature of 300 to 400 degrees C.  
     
     
         3 . A semiconductor memory device production method as claimed in  claim 1 , wherein if the noble metal upper electrode is formed by the CVD method, the anneal is performed after formation of the high dielectric insulation film.  
     
     
         4 . A semiconductor memory device production method as claimed in  claim 2 , wherein if the noble metal upper electrode is formed by the CVD method, the anneal is performed after formation of the high dielectric insulation film.  
     
     
         5 . A semiconductor memory device production method as claimed in  claim 1 , wherein the high dielectric insulation film is a (Ba, Sr)TiO 3  film or Pb(Zr, Ti)O 3  film.  
     
     
         6 . A semiconductor memory device production method as claimed in  claim 2 , wherein the high dielectric insulation film is a (Ba, Sr)TiO 3  film or Pb(Zr, Ti)O 3  film.  
     
     
         7 . A semiconductor memory device production method as claimed in  claim 1 , wherein the noble metal is Ru, Ir, or Pt.  
     
     
         8 . A semiconductor memory device production method as claimed in  claim 2 , wherein the noble metal is Ru, Ir, or Pt.  
     
     
         9 . A semiconductor memory device production method as claimed in  claim 1 , wherein the capacitor is formed by: a step of processing the noble metal lower electrode into a desired shape by RIE treatment; a step of forming a high dielectric insulation film at the substrate temperature of 200 degrees C by using the CVD method; a step of crystallizing the high dielectric insulation film by the RTA treatment of 700 degrees C in nitrogen; and a step of forming the noble metal upper electrode.  
     
     
         10 . A semiconductor memory device production method as claimed in  claim 2 , wherein the capacitor is formed by: a step of processing the noble metal lower electrode into a desired shape by RIE treatment; a step of forming a high dielectric insulation film at the substrate temperature of 200 degrees C by using the CVD method; a step of crystallizing the high dielectric insulation film by the RTA treatment of 700 degrees C in nitrogen; and a step of forming the noble metal upper electrode.