Silicon on insulator transistor structure for imbedded DRAM

Abstract

To address the above-discussed deficiencies of the prior art, the present invention provides an integrated circuit formed on a semiconductor wafer, comprising a doped base substrate; an insulator layer formed over the doped base substrate; and a doped ultra thin active layer formed on the insulator layer, the ultra thin active layer including a gate oxide, a gate formed on the gate oxide, and source and drain regions formed in the ultra thin active layer and adjacent the gate. The present invention therefore provides a semiconductor wafer that provides a doped ultra thin active layer. The lower Ioff in the DRAM transistor allows for lower heat dissipation, and the overall power requirement is decreased. Thus, the present invention provides a lower Ioff with reasonably good ion characteristics.

What is claimed is:  
     
         1 . An integrated circuit formed on a semiconductor wafer, comprising: 
 a doped base substrate;    an insulator layer formed over the doped base substrate; and    a doped ultra thin active layer formed on the insulator layer, the ultra thin active layer including a gate oxide, a gate formed on the gate oxide, and source and drain regions formed in the ultra thin active layer and adjacent the gate.    
     
     
         2 . The integrated circuit as recited in  claim 1  wherein the ultra thin active layer has a thickness ranging from about 10 nm to about 25 nm.  
     
     
         3 . The integrated circuit as recited in  claim 1  wherein the ultra thin active layer forms an active layer of a dynamic random access memory (DRAM) device.  
     
     
         4 . The integrated circuit as recited in  claim 3  wherein the DRAM device is a high density DRAM device.  
     
     
         5 . The integrated circuit as recited in  claim 1  wherein the ultra thin active layer is doped with a P-type dopant and the source and drain regions are doped with an N-type dopant.  
     
     
         6 . The integrated circuit as recited in  claim 1  wherein the insulator is silicon dioxide and has a thickness of at least about 0.5 μm.  
     
     
         7 . The integrated circuit as recited in  claim 1  wherein the base substrate is a heavily doped substrate having a dopant concentration of at least about 10 17  atoms/cm 3 .  
     
     
         8 . A high density dynamic random access memory (DRAM) device formed on a semiconductor wafer, comprising; 
 a plurality of transistors; and    a plurality of DRAM transistors, at least one of the DRAM transistors electrically connected to at least one of the plurality of transistors and at least one of the DRAM transistors including: 
 a doped base substrate;  
 an insulator layer formed over the doped base substrate; and  
 a doped ultra thin active layer formed on the insulator layer, the ultra thin active layer including a gate oxide, a gate formed on the gate oxide, and source and drain regions formed in the ultra thin active layer and adjacent the gate.  
   
     
     
         9 . The high density DRAM device as recited in  claim 8  wherein the ultra thin active layer has a thickness ranging from about 25 nm to about 10 nm.  
     
     
         10 . The high density DRAM device as recited in  claim 8  wherein the plurality of transistors includes at least one complementary metal oxide semiconductor (CMOS) transistor.  
     
     
         11 . The high density DRAM device as recited in  claim 8  wherein the ultra thin active layer is doped with an N-type dopant and the source and drain regions are doped with a P-type dopant.  
     
     
         12 . The high density DRAM device as recited in  claim 8  wherein the ultra thin active layer is doped with a P-type dopant and the source and drain regions are doped with an N-type dopant.  
     
     
         13 . The high density DRAM device as recited in  claim 8  wherein the insulator is silicon dioxide and has a thickness of at least about 0.5 μm.  
     
     
         14 . The high density DRAM device as recited in  claim 8  wherein the base substrate is a heavily doped substrate having a dopant concentration of at least about 10 17  atoms/cm 3 .  
     
     
         15 . A method of fabricating an integrated circuit located on a semiconductor wafer, comprising: 
 forming doped base substrate;    forming an insulator layer over the doped base substrate; and    forming a doped ultra thin active layer on the insulator layer, the ultra thin active layer including a gate oxide, a gate formed on the gate oxide, and source and drain regions formed in the ultra thin active layer and adjacent the gate.    
     
     
         16 . The method as recited in  claim 15  wherein forming a doped ultra thin active layer includes forming the ultra thin active layer to a thickness ranging from about 25 nm to about 10 nm.  
     
     
         17 . The method as recited in  claim 15  wherein forming an ultra thin active layer includes forming an active layer of a dynamic random access memory (DRAM) device.  
     
     
         18 . The method as recited in  claim 17  wherein forming an active layer of a DRAM device includes forming a high density DRAM device.  
     
     
         19 . The method as recited in  claim 15  wherein forming an ultra thin active layer includes doping the ultra thin active layer with a P-type dopant and doping the source and drain regions with an N-type dopant.  
     
     
         20 . The method as recited in  claim 15  wherein forming an insulator includes forming a silicon dioxide layer to a thickness of at least about 0.5 μm.  
     
     
         21 . The method as recited in  claim 15  wherein forming a base substrate includes forming a heavily doped substrate having a dopant concentration of at least about 10 17  atoms/cm 3 .