Method of manufacturing semiconductor device

Abstract

In a method of manufacturing a semiconductor device having first through third MOS transistors, using a first mask ( 311 ), wells ( 313, 314 ) and first threshold adjustment regions ( 315, 316 ) are formed at transistor areas ( 306 n, 308 n ) for the second and the third MOS transistors in a semiconductor substrate ( 301 ). Next, using a second mask ( 319 ), second threshold adjustment regions ( 320, 321 ) are formed at transistor areas ( 304 n and 308 n ) for the first and the third MOS transistors. In the transistor area for the third MOS transistor, both of the first threshold adjustment region and the second threshold adjustment region form a third adjustment region. Thus, using the two masks, three thresholds of the MOS transistors are obtained.

What is claimed is:  
     
         1 . A method of manufacturing semiconductor device having first, second and third MIS transistors on a semiconductor substrate, said first MIS transistor having a first threshold, said second MIS transistor having a second threshold higher than said first threshold, said third MIS transistor having a third threshold higher than said second threshold, said method comprising the steps of: 
 depositing a first mask on said semiconductor substrate at a first area for said first MIS transistor;    introducing first impurities into said semiconductor substrate to form wells at second and third areas for said second and said third MIS transistors;    successively, introducing second impurities into said wells to form first threshold adjustment regions for said second threshold;    depositing a second mask on said semiconductor substrate at said second area for said second MIS transistor after removing the first mask; and    introducing third impurities into said semiconductor substrate to form second threshold adjustment regions for said first threshold at said first and said third areas, one of said second threshold adjustment regions serving as a third threshold adjustment region for said third threshold together with one of said first threshold adjustment regions at said third area.    
     
     
         2 . A method of manufacturing semiconductor device having first, second and third MIS transistors in a semiconductor substrate, said first MIS transistor having a first threshold, said second MIS transistor having a second threshold higher than said first threshold, said third MIS transistor having a third threshold higher than said second threshold, said method comprising the steps of: 
 defining first, second and third areas corresponding to said first, said second and said third MIS transistors, respectively, on a surface of said semiconductor substrate;    depositing a first mask having first and second opening windows corresponding to said second and said third areas, respectively, on said surface of said semiconductor substrate;    introducing first impurities into said semiconductor substrate through said first and said second opening windows to form wells at said second and said third areas at the same time;    successively introducing second impurities into said wells through said first and said second opening windows to form first threshold adjustment regions for said second threshold at the same time;    completely removing said first mask from said surface of said semiconductor substrate;    depositing a second mask having third and fourth opening windows corresponding to said first and said third areas, respectively, on said surface of said semiconductor substrate; and    introducing third impurities into said semiconductor substrate through said third and said fourth opening windows to form second threshold adjustment regions for said first threshold at the same time, one of said second threshold adjustment regions serving as a third threshold adjustment region for said third threshold together with one of said first threshold adjustment regions at said third area.    
     
     
         3 . A method as claimed in  claim 2 , wherein said third and said fourth opening windows are smaller than said first and said third areas, respectively.  
     
     
         4 . A method as claimed in  claim 3 , wherein said third and said fourth opening windows correspond to gate areas of said first and said third MIS transistors, respectively.  
     
     
         5 . A method as claimed in  claim 3 , wherein said second opening window has the same size as that of said fourth opening windows.  
     
     
         6 . A method as claimed in  claim 2 , wherein each of the introducing steps is carried out by ion plantation.  
     
     
         7 . A method as claimed in  claim 2 , wherein said MIS transistors are MOS transistors.  
     
     
         8 . A method as claimed in  claim 7 , wherein each of said MOS transistors is one of MOS transistors forming a CMOS transistor.  
     
     
         9 . A method of manufacturing semiconductor device having first, second and third MOS transistors having a first conductive type and fourth, fifth and sixth MOS transistors having a second conductive type different from said first conductive type, said first and said forth MOS transistors forming a first CMOS transistor having a first threshold, said second and said fifth MOS transistors forming a second CMOS transistor having a second threshold higher than said first threshold, said third and said sixes MOS transistors forming a third CMOS transistor having a third threshold higher than said second threshold, said method comprising the steps of: 
 defining first through sixth areas corresponding to first through sixth MOS transistors, respectively, on a surface of said semiconductor substrate;    depositing a first mask having first and second opening windows corresponding to said second and said third areas, respectively, on said surface of said semiconductor substrate;    introducing first impurities of the second conductive type into said semiconductor substrate through said first and said second opening windows to form first wells in said second and said third areas at the same time;    successively introducing second impurities of the second conductive type into said first wells through said first and said second opening windows to form first threshold adjustment regions for said second threshold at the same time;    completely removing said first mask from said surface of said semiconductor substrate;    depositing a second mask having third and fourth opening windows corresponding to said first and said third areas, respectively, on said surface of said semiconductor substrate;    introducing third impurities of the second conductive type into said semiconductor substrate through said third and said fourth opening windows to form second threshold adjustment regions for said third threshold at the same time, one of said second threshold adjustment regions serving as a third threshold adjustment region for said third threshold together with one of said first threshold adjustment regions at third area,    completely removing said second mask from said surface of said semiconductor substrate;    depositing a third mask having fifth and sixth opening windows corresponding to said fourth and said sixth areas, respectively, on said surface of said semiconductor substrate;    introducing fourth impurities of the first conductive type into said semiconductor substrate through said fifth and said sixth opening windows to form second wells in said fourth and said sixth areas at the same time;    successively introducing fifth impurities of the first conductive type into said second wells through said fifth and said sixth opening windows to form fourth threshold adjustment regions for said first threshold at the same time;    completely removing said third mask from said surface of said semiconductor substrate;    depositing a fourth mask having seventh and eighth opening windows corresponding to said fifth and said sixth areas, respectively, on said surface of said semiconductor substrate;    introducing sixth impurities of the first conductive type into said semiconductor substrate through said seventh and said eighth opening windows to form third wells in said fifth and said sixth areas at the same time; and    successively introducing seventh impurities of the first conductive type into said semiconductor substrate through said seventh and said eighth opening windows to form fifth threshold adjustment regions for said second threshold in said third wells at the same time, one of said fifth threshold adjustment regions serving as a sixth threshold adjustment region for said third threshold together with one of said fourth threshold adjustment regions at sixth area.    
     
     
         10 . A method as claimed in  claim 9 , wherein said third and said fourth opening windows are smaller than said first and said third areas, respectively.  
     
     
         11 . A method as claimed in  claim 10 , wherein said third and said fourth opening windows correspond to gate areas of said first and said third MOS transistors, respectively.  
     
     
         12 . A method as claimed in  claim 10 , wherein said second opening window has the same size as that of said fourth opening windows.  
     
     
         13 . A method as claimed in  claim 9 , wherein said eighth opening window is smaller than said sixth area.  
     
     
         14 . A method as claimed in  claim 14 , wherein said eighth opening window correspond to a gate area of said sixth MOS transistors.  
     
     
         15 . A method as claimed in  claim 9 , wherein each of the introducing steps is carried out by ion plantation.  
     
     
         16 . A semiconductor device comprising: 
 a first MIS transistor having a first source region, a first drain region, a first threshold adjustment region, and a first threshold;    a second MIS transistor having a second source region, a second drain region, a second threshold adjustment region, and a second threshold higher than said first threshold; and    a third MIS transistor having a third source region, a third drain region, a third threshold adjustment region, and a third threshold higher than said second threshold; wherein    said first threshold adjustment region is apart from both of said first source region and said first drain region;    said second threshold adjustment region being in contact with both of said second source region and said second drain region; and    said third threshold adjustment region being in contact with both of said third source region and said third drain region.    
     
     
         17 . A semiconductor device as claimed in  claim 16 , said third threshold adjustment region having a first impurity density region and second impurity density regions adjoining to said first impurity density region, said first impurity density region having a first impurity density, each of said second impurity density regions having a second impurity density lower than said first impurity density, wherein 
 said third source region and said third drain region are in contact with said second impurity density regions, respectively, and apart from said first impurity density region.    
     
     
         18 . A semiconductor device as claimed in  claim 16 , wherein said MIS transistors are MOS transistors.  
     
     
         19 . A semiconductor device as claimed in  claim 18 , wherein each of said MOS transistors is one of MOS transistors forming a CMOS transistor.  
     
     
         20 . A semiconductor device comprising: 
 a first MOS transistor having a first source region, a first drain region, a first threshold adjustment region, and a first conductive type;    a second MOS transistor having a second source region, a second drain region, a second threshold adjustment region, and said first conductive type;    a third MOS transistor having a third source region, a third drain region, a third threshold adjustment region, and said first conductive type;    a fourth MOS transistor having a fourth source region, a fourth drain region, a fourth threshold adjustment region, and a second conductive type, and forming a first CMOS transistor having a first threshold together with said first MOS transistor;    a fifth MOS transistor having a fifth source region, a fifth drain region, a fifth threshold adjustment region, and said second conductive type, and forming a second CMOS transistor having a second threshold higher than said first threshold together with said second MOS transistor; and    a sixth MOS transistor having a sixth source region, a sixth drain region, a sixth threshold adjustment region, and said second conductive type, and forming a third CMOS transistor having a third threshold higher than said second threshold together with said third MOS transistor; wherein    said first threshold adjustment region is apart from both of said first source region and said first drain region;    said second through said sixth threshold adjustment regions being in contact with said second through said sixth source regions and with said second through said sixth drain regions, respectively.    
     
     
         21 . A semiconductor device as claimed in claim  20 , said third threshold adjustment region having a first impurity density region and second impurity density regions adjoining to said first impurity density region, said first impurity density region having a first impurity density, each of said second impurity density regions having a second impurity density lower than said first impurity density, said sixth threshold adjustment region having a third impurity density region and fourth impurity density regions adjoining to said third impurity density region, said third impurity density region having a third impurity density, each of said fourth impurity density regions having a fourth impurity density lower than said third impurity density, wherein 
 said third source region and said drain region are in contact with said second impurity density regions, respectively, and apart from said first impurity density region, and    said sixth source region and said sixth drain region are in contact with said fourth impurity density regions, respectively, and apart from said third impurity density region.