Semiconductor integrated circuit

Abstract

Transistors are supplied with either a first power supply voltage or a second power supply voltage lower than the first power supply voltage. During an operation period of the transistors, substrate voltages of the transistors are set at a value between the first power supply voltage and the second power supply voltage. The substrate voltages are changed to lower threshold voltages of the transistors so that the transistors improve in drivability and operating speed. Therefore, neither a booster for generating higher voltages nor a pumping circuit for generating negative voltages is particularly required. This allows a reduction in layout size. Besides, in accordance with the operating state of the semiconductor integrated circuit, the transistor characteristics can be easily changed by changing the threshold voltages of the transistors.

What is claimed is:  
     
         1 . A semiconductor integrated circuit comprising transistors being supplied with, as substrate voltage(s), at least one of a first power supply voltage and a second power supply voltage lower than the first power supply voltage, and wherein 
 said substrate voltages of said transistors are set at a value between said first and second power supply voltages during an operation period of said transistors.    
     
     
         2 . The semiconductor integrated circuit according to  claim 1 , wherein 
 said substrate voltages are set at a value at the center of said first and second power supply voltages during said operation period.    
     
     
         3 . The semiconductor integrated circuit according to  claim 1 , wherein 
 said substrate voltages are set at one of said first and second power supply voltages during a non-operation period of said transistors.    
     
     
         4 . The semiconductor integrated circuit according to  claim 1 , wherein said transistors further comprise: 
 a pMOS transistor which is supplied with said first power supply voltage at its source electrode, and whose substrate voltage is set at a value between said first and second power supply voltages during said operation period; and    an nMOS transistor which is supplied with said second power supply voltage at its source electrode, and whose substrate voltage is set at a value between said first and second power supply voltages during said operation period.    
     
     
         5 . The semiconductor integrated circuit according to  claim 4 , wherein 
 said pMOS transistor and said nMOS transistor have lower forward biases between the transistors' respective sources and substrates during said operation period than a built-in potential of pn junctions between the sources and substrates.    
     
     
         6 . The semiconductor integrated circuit according to  claim 5 , wherein 
 said substrate voltage of said pMOS transistor and said substrate voltage of said nMOS transistor are set at a value at the center of said first and second power supply voltages during said operation period.    
     
     
         7 . The semiconductor integrated circuit according to  claim 4 , wherein 
 said substrate voltage of said pMOS transistor and said substrate voltage of said nMOS transistor are set equal to each other during said operation period.    
     
     
         8 . The semiconductor integrated circuit according to  claim 4 , wherein 
 said substrate voltage of said pMOS transistor and said substrate voltage of said nMOS transistor are respectively set at said first and second power supply voltages during a non-operation period.    
     
     
         9 . The semiconductor integrated circuit according to  claim 8 , wherein 
 when said substrate voltage of said pMOS transistor is set at said first power supply voltage, a voltage higher than said first power supply voltage is temporarily supplied to said substrate of said PMOS transistor.    
     
     
         10 . The semiconductor integrated circuit according to  claim 9 , further comprising a capacitor: 
 being charged by applying a voltage higher than said first power supply voltage; and    being connected to said substrate of said pMOS transistor when said substrate voltage of said pMOS transistor is set at said first power supply voltage.    
     
     
         11 . The semiconductor integrated circuit according to  claim 8 , wherein 
 when said substrate voltage of said nMOS transistor is set at said second power supply voltage, a voltage lower than said second power supply voltage is temporarily supplied to said substrate of said nMOS transistor.    
     
     
         12 . The semiconductor integrated circuit according to  claim 11 , comprising a capacitor being charged by applying a voltage lower than said second power supply voltage, and  
       wherein said capacitor is connected to said substrate of said nMOS transistor when said substrate voltage of said nMOS transistor is set at said second power supply voltage.  
     
     
         13 . The semiconductor integrated circuit according to  claim 4 , wherein 
 said substrate of said pMOS transistor and said substrate of said nMOS transistor are connected to each other during said operation period.    
     
     
         14 . The semiconductor integrated circuit according to  claim 4 , wherein 
 said substrate of said pMOS transistor and said substrate of said nMOS transistor are connected to each other during said operation period, the substrates being charged by applying different voltages.    
     
     
         15 . The semiconductor integrated circuit according to  claim 1 , further comprising a capacitor being charged by applying a predetermined voltage, and wherein 
 said capacitor is connected to said substrates of said transistors during said operation period.    
     
     
         16 . A semiconductor integrated circuit comprising an nMOS transistor, whose substrate is supplied with an external power supply voltage until the external power supply voltage reaches a predetermined value.  
     
     
         17 . A semiconductor integrated circuit comprising an nMOS transistor, whose substrate is supplied with an internal power supply voltage which is generated from an external power supply voltage until the internal power supply voltage reaches a predetermined value.  
     
     
         18 . A semiconductor integrated circuit comprising a pMOS transistor, whose substrate is supplied with a ground voltage until an external power supply voltage reaches a predetermined value.  
     
     
         19 . A semiconductor integrated circuit comprising a pMOS transistor, whose substrate is supplied with a ground voltage until an internal power supply voltage which is generated from an external power supply voltage reaches a predetermined value.