Semiconductor device and method for fabricating the same

Abstract

A semiconductor device of this invention includes a first interconnect pattern formed on a semiconductor substrate and a second interconnect pattern formed above the first interconnect pattern with an interlayer insulating film sandwiched therebetween. The first interconnect pattern includes a dummy pattern insulated from the first interconnect pattern, and the dummy pattern includes a plurality of fine patterns adjacent to each other and air gaps formed between the adjacent fine patterns.

What is claimed is:  
     
         1 . A semiconductor device comprising: 
 a first interconnect pattern formed on a semiconductor substrate; and    a second interconnect pattern formed above said first interconnect pattern with an interlayer insulating film sandwiched therebetween,    wherein said first interconnect pattern includes a dummy pattern electrically insulated from said first interconnect pattern, and    said dummy pattern includes a plurality of fine patterns adjacent to each other and air gaps sandwiched between said adjacent fine patterns.    
     
     
         2 . The semiconductor device of  claim 1 , 
 wherein air gaps are provided between adjacent patterns of said first interconnect pattern.    
     
     
         3 . The semiconductor device of  claim 1 , 
 wherein said dummy pattern is formed in a region on said semiconductor substrate where said first interconnect pattern is relatively sparse.    
     
     
         4 . A method for fabricating a semiconductor device comprising: 
 a first step of forming a first interconnect pattern forming layer from a conducting film on a semiconductor substrate and a first insulating film on said first interconnect pattern forming layer;    a second step of forming a plug electrically connected to said first interconnect pattern forming layer by forming an opening in said first insulating film by selective etching and filling said opening with a conducting film;    a third step of forming a resist pattern corresponding to a first interconnect pattern including a dummy pattern from a resist film applied over said semiconductor substrate including said plug;    a fourth step of patterning said first insulating film by etching said first insulating film with said resist pattern and said plug used as a mask;    a fifth step of forming, from said first interconnect pattern forming layer, said first interconnect pattern and said dummy pattern that is electrically insulated from said first interconnect pattern and includes a plurality of fine patterns adjacent to each other by etching said first interconnect pattern forming layer with said resist pattern and said plug used as a mask;    a sixth step of forming, on said semiconductor substrate, a second insulating film covering said plug, said first interconnect pattern and said dummy pattern so as to form air gaps between patterns of said first interconnect pattern and between said fine patterns of said dummy pattern; and    a seventh step of planarizing a top face of said second insulating film until said plug is exposed and forming, on said second insulating film, a second interconnect pattern electrically connected to said plug after planarization.    
     
     
         5 . The method for fabricating a semiconductor device of  claim 4 , 
 wherein said first step includes a sub-step of forming an underlying insulating film on said semiconductor substrate before forming said first interconnect pattern forming layer, and    the method further includes, between said fifth step and said sixth step, a step of trenching an upper portion of said underlying insulating film by etching said underlying insulating film with said resist pattern and said plug used as a mask.    
     
     
         6 . A method for fabricating a semiconductor device comprising: 
 a first step of forming a first interconnect pattern forming layer of a conducting film on a semiconductor substrate;    a second step of forming a resist pattern corresponding to a first interconnect pattern including a dummy pattern from a resist film applied over said semiconductor substrate;    a third step of forming, from said first interconnect pattern forming layer, said first interconnect pattern and said dummy pattern that is electrically insulated from said first interconnect pattern and includes a plurality of fine patterns adjacent to each other by etching said first interconnect pattern forming layer with said resist pattern used as a mask;    a fourth step of forming, on said semiconductor substrate, an insulating film covering said first interconnect pattern and said dummy pattern so as to form air gaps between said fine patterns of said dummy pattern;    a fifth step of planarizing a top face of said insulating film and forming a plug electrically connected to said first interconnect pattern by forming an opening in said insulating film after planarization by selective etching and filling said opening with a conducting film; and    a sixth step of forming, on said insulating film, a second interconnect pattern electrically connected to said plug.