Memory cell, method of controlling same and method of manufacturing same

Abstract

A DRAM memory cell includes a cell transistor ( 91 a ) having a source/drain region ( 6 a ) connected to a lower electrode ( 15 ) of a capacitor ( 18 a ) through a pad ( 10 a ) and a storage node ( 11 a ). During a pause, the lower electrode ( 15 ) is not depleted, but at least one of the pad ( 10 a ) and the storage node ( 11 a ) is depleted to increase a voltage drop therein. The voltage drop alleviates an electric field at a gate end of the transistor ( 91 a ) to reduced a TAT (Trap Assisted Tunneling) induced leakage current. The DRAM memory cell is provided which decreases a leakage current from the capacitor and increases time intervals between refresh operations, or refresh pause time.

What is claimed is:  
     
         1 . A memory cell comprising: 
 a cell transistor having a pair of source/drain regions and a gate electrode;    a first semiconductor layer provided on one of said source/drain regions and having a first impurity concentration ranging from about 5×10 17 /cm 3  to about 1×10 20 /cm 3 ;    a second semiconductor layer provided on said first semiconductor layer and having a second impurity concentration of not less than about 4×10 20 /cm 3 ;    a dielectric layer provided on said second semiconductor layer; and    an electrode, in conjunction with said dielectric layer and said second semiconductor layer, constituting a capacitor, said second semiconductor layer serving as a counter electrode to said electrode.    
     
     
         2 . The memory cell according to  claim 1 , further comprising 
 an interlayer insulation film for providing isolation between said capacitor and said cell transistor,    wherein said first semiconductor layer includes a storage node extending through said interlayer insulation film, and a pad between said storage node and said one of said source/drain regions.    
     
     
         3 . The memory cell according to  claim 1 , 
 wherein said first semiconductor layer is depleted during a pause period over which said capacitor holds electric charge without being refreshed.    
     
     
         4 . A memory cell comprising: 
 a cell transistor having a pair of source/drain regions and a gate electrode;    a first interlayer insulation film formed on said cell transistor;    a first conductor extending through said first interlayer insulation film and provided on one of said source/drain regions;    a second interlayer insulation film isolated from said cell transistor by said first interlayer insulation film;    a second conductor extending through said second interlayer insulation film and formed on said first conductor; and    a capacitor connected to said first conductor through said second conductor.    
     
     
         5 . A memory cell comprising: 
 a first transistor having a pair of source/drain regions provided in an upper surface of a semiconductor substrate, and a gate electrode opposed to said semiconductor substrate with a first insulation film therebetween;    a capacitor opposed to said first transistor with an interlayer insulation film therebetween in a depth direction of said semiconductor substrate, said capacitor being connected to one of said source/drain regions of said first transistor; and    a second transistor disposed in said interlayer insulation film between said one of said source/drain regions of said first transistor and said capacitor, said second transistor having a pair of source/drain regions stacked in the depth direction of said semiconductor substrate.    
     
     
         6 . The memory cell according to  claim 5 , 
 wherein said first transistor and said second transistor are of the same conductivity type; and    wherein said gate electrode of said first transistor has a sidewall covered with a second insulation film, and said pair of source/drain regions of said second transistor are disposed adjacent to said gate electrode of said first transistor with said second insulation film therebetween.    
     
     
         7 . The memory cell according to  claim 5 , 
 wherein said second transistor further has a gate electrode provided over said first transistor, and a second insulation film for covering a sidewall of said gate electrode of said second transistor; and    wherein said pair of source/drain regions of said second transistor are disposed adjacent to said gate electrode of said second transistor with said second insulation film therebetween.    
     
     
         8 . The memory cell according to  claim 5 , further comprising 
 a semiconductor layer for establishing a connection between one of said source/drain regions of said second transistor and said capacitor,    wherein said second transistor further has a second insulation film disposed adjacent to said pair of source/drain regions of said second transistor, and    wherein a surface of said semiconductor layer in contact with said second insulation film is doped with at least one of nitrogen and hydrogen.    
     
     
         9 . The memory cell according to  claim 6 , 
 wherein a surface of said second insulation film in contact with said pair of source/drain regions of said second transistor is doped with oxygen.