Flash memory and methods of writing and erasing the same as well as a method of forming the same

Abstract

A flash memory is provided on a semiconductor substrate. A trench with corners is provided on a surface of the semiconductor substrate. A gate insulation film is provided on a surface within the trench. A floating gate is buried within the trench through the gate insulation film. A control gate is provided isolated from the floating gate, and also is characterized in that at the corners of the trench, corners of the floating gate face through the gate insulation film to edges of the semiconductor substrate, and if the control gate is made low potential whilst the semiconductor substrate is made high potential, then electrons are extracted from the corners of the floating gate.

What is claimed is:  
     
         1 . A method of forming a floating gate comprising the steps of: 
 forming a first insulating film on a surface of a semiconductor substrate;    selectively forming a mask on said first insulating film;    selectively etching said first insulating film and said semiconductor substrate by using said mask to form a trench in said semiconductor substrate;    removing said mask;    forming a second insulating film on said first insulating film and also on side walls and a bottom of said trench; and    forming an electrically conductive film on said second insulating film to form a floating gate,    said floating gate in said trench being isolated by said second insulating film from said semiconductor substrate, and    said floating gate being isolated by laminations of said first and second insulating films from said semiconductor substrate, to suppress electron injections to said floating gate from top corners of said trench.    
     
     
         2 . The method as claimed in  claim 1 , wherein said step of forming said electrically conductive film comprises depositing said electrically conductive film to completely fill said trench.  
     
     
         3 . The method as claimed in  claim 2 , further comprising the step of: 
 patterning said electrically conductive film to shape said floating gate extending in said trench and over peripheral regions on top portions of said trench.    
     
     
         4 . A method of forming a semiconductor device comprising the steps of: 
 forming a first insulating film on a surface of a semiconductor substrate;    selectively forming a mask on said first insulating film;    selectively etching said first insulating film and said semiconductor substrate by using said mask to form a trench in said semiconductor substrate;    removing said mask;    forming a second insulating film on said first insulating film and also on side walls and a bottom of said trench;    forming an electrically conductive film on said second insulating film to form a floating gate, wherein said floating gate in said trench is isolated by said second insulating film from said semiconductor substrate, and wherein said floating gate over said semiconductor substrate is isolated by laminations of said first and second insulating films from said semiconductor substrate, to suppress electron injections to said floating gate from top corners of said trench;    forming a dielectric film on said electrically conductive film; and    forming a control gate electrode on said dielectric film, wherein said control gate electrode is electrically isolated by said dielectric film from said floating gate.    
     
     
         5 . The method as claimed in  claim 4 , wherein said step of forming said electrically conductive film comprises depositing said electrically conductive film to completely fill said trench.  
     
     
         6 . The method as claimed in  claim 5 , further comprising the step of: 
 patterning said floating gate into a first stripe shape in plan view, said first stripe shape having a first longitudinal direction, and said floating gate extending in said trench and over peripheral regions to top portions of said trench.    
     
     
         7 . The method as claimed in  claim 6 , further comprising the step of: 
 patterning said control gate electrode into a second stripe shape in plan view, said second stripe shape having a second longitudinal direction perpendicular to said first longitudinal direction, said control gate electrode being isolated from said surface of said semiconductor substrate by laminations of said dielectric film, said first and said second insulating films.